I’m developing the prototype of a power inverter topology. Each prototype PCB carries eight ADuM5240 devices that create isolated rails for gate-drive circuitry.
1 · Observed behaviour
| Timeline | VDD  GND DC-impedance (un-powered) |
IDD @ 5 V | Notes |
|---|---|---|---|
| Immediately after soldering | ~20 kΩ (expected) | 80 – 100 mA (within spec) | Verified on multiple boards |
| After 3-7 days (board idle, powered or un-powered) | 10 – 100 Ω (unexpected) | ≫ 100 mA → rail droops | All eight devices eventually shift |
Reproduced on two boards
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Board A – powered/tested for a week, then stored in an ESD bag → fault one week later.
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Board B – never powered, only assembled & stored → same fault after ~1 week.
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No other IC on the board shows this behaviour.
2 · Assembly / rework conditions
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Pb-free reflow: peak ≈ 260 °C, ~45 s above 245 °C (6-layer board).
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Replacements: hot-air ≈ 400 °C for ≤ 30 s.
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Touch-ups: soldering iron 400 °C.
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No conformal coat; storage in anti-static bags with desiccant at ~25 °C, 50 % RH.
3 · Questions
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Is a delayed drop of VDD-to-GND impedance into the sub-100 Ω range a recognized failure mode for the ADuM5240?
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Could the 260 °C reflow peak, 400 °C hot-air, or 400 °C iron introduce latent damage that manifests days later?
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Are there recommended storage or moisture-sensitivity precautions (bake-out, conformal coating, etc.) to prevent this degradation?
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Once impedance collapses, is the device permanently damaged, or can it be recovered?
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Any board-level mitigations you’d suggest (layout tweaks, decoupling, inrush limiting)?
Thank you for your assistance.
