422MHz EMI ISSUE

While the data isolator portion of the module can generate emissions, it is much more likely that the emissions source is the LTM2881's isolated power supply.

Be sure to follow the guidance on PCB layout in the datasheet's pages 16 - 19.

The isolated power supply can be considered as a high frequency current source which is injecting common-mode current into the dipole antenna formed by the two voltage domains of the isolated (input/processor side and output/cable side). 

In this situation, the radiated emissions mitigation technique consists of two strategies - 1. shorting the dipole antenna by providing an alternative path for the common-mode current to flow by using stitching capacitance across the isolation barrier and 2. detuning the dipole antenna structure by reducing the size of one of the antenna "arms" by placing ferrites in all signal and power (including "ground2") nets. 

The DC1746A eval board implements the first strategy with the combination of the two series 470pf Y-capacitors connected across the isolation barrier in conjunction with a capacitor formed by the PCB structure's parasitic capacitance between the overlap of top and bottom layers.

The second strategy incorporates a ferrite filter plate between the PCB and the connector.  While this worked fine in the evaluation board, a more common implementation of this strategy would be to place ferrite beads in series with all signals on the isolated side.  The area between the uModule and the ferrite beads should be minimized (unless it is forming part of a plate of the PCB stitching capacitor).  When laying out the PCB/ferrite footprint, make sure to keep all copper away from the ferrite on ALL layers - having copper under the ferrite creates a parasitic capacitance which will short the ferrite at the higher frequencies you're wanting the ferrite to block.

Note that the effective series inductance of the stitching capacitor and the capacitance form a resonance which can be in the 400-600MHz region depending on the effective C & L values.  This inductance is a combination of the physical capacitor's parasitic ESL and the PCB layout's path inductance which is impacted by trace routing/shape and location / number of via's if present.

Eric