ESD Protection

Hello Emirhankose,

  The quick answer to all of your questions is basically it depends.

   As you describe your initial test, it sounds like you are applying the ESD voltage stress primarily across the isolation barrier since the ESD gun's reference is connected to "GND" and you're zapping one of the bus pins.  The ESD energy is flowing into the pin you're zapping and then flowing through the isolation barrier's capacitance and then spreading out through the board's circuit connected to the transceiver's input pins until it finds a path back through to the GND and the ESD gun's reference.   Because you're only zapping one of the transceiver's bus pins, the TVS diodes are helping to keep all of the bus pins within their clamp voltage which does provide some protection; however, the common mode currents from the ESD pulse are still causing damage elsewhere.

   In terms of what to do/how to fix, a successful ESD protection network is really a system level design problem which will take into account the full system and the type and application of the ESD stress you need to protect against.  Not having all of this information (and its likely not appropriate for you to share this information in this forum so I'm not asking), makes giving specific design guidance challenging so I'll give some general background and a suggested starting point.

  In a big picture, ESD protection is basically redirecting the energy in the ESD pulse away from the protected part while limiting the peak voltage to remain within the part's ABSMAX ratings.  In general EMC protective networks will generally look like a pi-type of network (shunt element -series element - shunt element) or simply some portion of it (e.g. shunt or shunt + series) depending on the level of protection needed.  What specific strategies and part selections will depend on the type and level of ESD stress being applied as well as how its applied.  You also need to take into account your isolation requirements since the protection strategy needs to be able to accommodate the expected operating conditions (e.g. normal working voltage potentials between the bus pins and earth ground). 

  Physical layout is also important.  For example, a GDT could reasonably be part of a input clamping shunt strategy that is electrically connected as shown in your block diagram; however, I would not suggest physically connecting it directly to the transceiver's GND1 pin as the diagram might suggest (even it ultimately is connected to the system or chassis "ground").  Instead, I'd suggest physically connecting the shunt protective device (GDT or parallel RC) directly between GND2 and the system or chassis GND right at the connector or terminals.  This way when the currents flow, they are well away from the sensitive circuits.

  Of the different types of EMC disturbance, ESD is usually the less energetic and so often only the 1st shunt device of the pi-network is all that is needed (though this will depend on the ESD type & level as well as how much margin your application needs).   Because of the isolation, you can consider this protective shunt device as being formed from two series connected devices - the first half device shunts from the bus pins to GND2 and then the second half device shunts from GND2 to chassis/earth (or whatever the reference for the ESD strike is).

  In your diagram, the TVS diodes would be the first-half shunt and the second half shunt is the GDT.  I think TVS diodes are fine for the first half shunt; however, using a GDT as the second-half shunt would not be my first choice in this application.  The GDT will not conduct until the voltage across it has exceeded its trigger voltage and with the very fast rising edge of an ESD waveform, its quite possible that there will be significant voltage overshoot before the GDT reacts and actually starts to clamp the voltage.  A better choice might be to use a capacitor which has a suitable voltage rating based on your isolation requirements. The capacitor will look like a short circuit to the high frequency components of the ESD waveform and so be active well before the GDT will trigger.   There are special safety-rated capacitors (x or y caps) which would be appropriate for this application. Usually a resistor is included in parallel to the cap to provide a discharge path for the cap.  This resistor should be special pulse-rated resistor which is sized based on the expected ESD pulse energy.  Depending on your application's application requirements, there may be limitations on leakage current across the isolation barrier and this can limit the values of the capacitor and pulse resistor in order to keep the leakage current within permitted limits. 

Depending on your application's requirements for ESD, its possible that you may need to test with different connections of the ESD generator.   If this is the case, then you'll need to evaluate each scenario to see what the appropriate protection would be.  Its possible the same circuit works for all cases or you may need to add additional circuit(s) to cover specific scenario(s).

Eric

Hello, first of all, thank you for sharing this valuable information. When I add an RC parallel network between the reference of the ESD path (GND_ISO) and the reference of the ESD gun (i.e., GND and system ground), I believe that the resistor value should be in the mega-ohm range or higher in order to avoid compromising the DC isolation. Otherwise, the DC isolation would be lost. What would you recommend in this case?

Yes, a resistor value in the mega-ohm range would be typical.   The exact value will likely depend on your system level isolation requirements which often specify a maximum system wide leakage current at a voltage and frequency.  Depending on your system design, you could then allocate a leakage current budget for the different parts of the system and the allocation for the isolated transceiver would give you a max leakage current for the ESD protection from which you can get a minimum R (and max C). 

I have one more question regarding this topic. I need to place a Y capacitor between two isolated grounds. In this case, is it more critical to have a high or low capacitance value?
The reason I am asking is that, for example, when I use a 4.7nF capacitor (Y2 type), I also see that Y1 type capacitors are available but typically at lower capacitance values.
From my point of view, using a Y1 type capacitor would be more beneficial due to its higher safety rating.
However, I am not sure how to correctly determine the required capacitance value for this application. Could you please clarify the correct approach to select the appropriate value?

Again, it depends.   

You are adding the cap to help provide protection and the key equation for determining the protection level is the capacitor's voltage-current relationship (i=Cdv/dt).  This relationship defines the impact that the disturbance current has on the dv/dt as well as the peak expected voltage due to the transients energy (or delivered charge) and you'll select the C to keep the dv/dt and delta V within your limits for the expected transient.

You need a high enough value to meet the protective requirements that are driving the need to add the cap and a low enough value so that you're still meeting your isolation leakage current requirements.  You also need to select a value which exists, is in a physical package that fits in your design, has a suitable availability for your schedule and is not too expensive plus other unstated requirements...

Usually because of this tradeoff you're not going to be able to select "highest/best X" in each (or perhaps any) category.  Finding a design solution here is going to be more of finding the least worst or just good enough in most areas (and being able to accept what happens in the others).   This is a total system level design problem and its usually not easy to solve due to all of the conflicting requirements.  Usually a key portion of the "design" work to get to a solution in these situations will be on pushing back/adjusting requirements in such a way that the overall system goals are still achieved while allowing for a realizable solution/design.  As I mentioned earlier, this probably isn't the right forum for this type of system design work.

Eric