I2C output of LTC4331 at 0x00

Hello Osamu,

  This is not unexpected behavior for the LTC4331 and despite its appearance, it is allowed by the I2C standard since when SCL is low, the value of SDA can change / be indeterminant as long as the setup and hold times are respected relative to the SCL edges.   The LTC4331 meets these timings as is listed in its datasheet.

  Internally, the LTC4331 samples and retimes the SCL and SDA signals which are then processed by an I2C state machine in order to identify I2C events (Start condition, sample data 0, sample data 1, stop condition, etc.) and then the LTC4331 transmits their occurrence across the link.  The I2C state machine on the other side of the link uses the occurrence of these events and known timing parameters set by the speed bit configuration to recreate the I2C message event on its side.  The local-side LTC4331 only transmits sample data values across the link after the local side falling SCL edge because it needs to see the falling edge to distinguish between a data bit and a pending stop or repeated start condition which the local-side controller could generate at any time. 

  This means that the remote side, when driving the bus only has partial information about the local side bus and generates its waveform levels based on what was last sampled and then holds those levels for the assumed timing interval before releasing.  For example, the SDA line is only held low for the appropriate bit time based on its internal timing in order to prevent stalling the bus.  If it doesn't have an updated sample value, then the remote LTC4331 releases SDA until it has an updated data sample value.  For high SDA values, SDA is already high so there isn't a noticeable "glitch". 

Thus, differences in the timing between the I2C bus SCL, the link speed setting and the two LTC4331's internal clock/sampling, can result in "odd" looking waveforms on the remote side bus.  

Eric