Hi,
If DE, DI input status are kept constant(high or low) when the device is powered down, can we assure the status of Z and Y during the power down period?
For example, if DE is kept low, Z and Y are in high-Z mode when VCC is between 4.75V and 5.25V, then we power down the device, can we assure Z and Y are still in high-Z mode when VCC is between 0-4.75V?