Placement and Routing

Hi Abhishek,

  The magnetic coupling between the transformers in different ADI isolator parts is so minimal it is not a concern.  This can be proven by observing that the ADI isolators internally contain multiple transformers, typically using one transformer per data bit/channel. These transformers are fabricated adjacent to each other on the same die which will result in a much stronger coupling between the transformers on the die vs. between transformers in the different die of different parts.  Given that the transformers on the same die are able to operate without issue despite to their stronger coupling, there will be no problems with the weaker coupling between the transformers of different parts.  Therefore, the placement and orientation of the isolators will be dependent on other considerations such as routing efficiency, the board's assembly requirement/design for manufacturing, isolation requirements and EMC considerations.

  Having multiple isolators in a design, especially ones with integrated isolated power supplies, can be a challenging design problem when considering radiated emissions at a system level.  All isolated power supplies have some level of radiated emissions and increasing the number of them on a board will increase the total emissions and so additional care in layout and filtering may be required for these applications.   Circuits and layouts which are sufficient for a single device may need modifications / improvements when additional supplies are present.

   Carefully looking at your board's layout, based on the components and apparent trace connections, I infer that I'm only seeing one ADI CAN transceiver (U65) in what is shown.   Assuming U65 is an ADM3057E, I would be concerned about the apparent lack of a common mode filter in the output of the isolated power supply.  Please refer to the recommended PCB layout shown in Figure 33 of the AD3057E's datasheet.  For proper emissions reduction, it is crucial that the ferrites shown in the figure be used to connect the VISOOUT and GNDISO nets to the VISOIN and GND2 nets.  It is also important that the trace area of the VISOOUT and GNDISO nets between the ADM3057E and the ferrite terminals be as physically small as possible.  Finally so that the required inductance of the ferrites is not short-circuited by the parasitic capacitance formed between the ferrite and any adjacent copper, the PCB area under the ferrites (inductors) needs to be free of all copper.  Based on what I can see in the shared images, it doesn't appear that these considerations are present in the design and so, absent other mitigations I'm not aware of, my expectation is that this board may have problems passing most radiated emissions tests.

Eric

PS -  The other components (e.g. U122, U92, U104) do not appear to be ADI parts based on the layout of the adjacent parts and connections that are shown.  The layout does, however, appear to be what I'd expect for the layout of another company's full-duplex RS-485 transceivers.  Assuming this is correct, you'll need to pursue support for these parts in other forums.

Thanks Eric for your  response.

Please also suggest that if we can place these ICs adjacent on Top and Bottom side as shown in Image 3.

Can you please also share the related documents such as reference layout design or EMI tests related to ADM3057E or similar ICs?

Additional information is available in the application note AN-0971. 

Note that the input-output dipole radiation (figure 4 in the application note) can also be minimized by reducing the area/size of the dipole leg.   This method is implemented in the recommended PCB layout in the ADM3057E's datasheet with the inclusion of the ferrite beads in the power supply nets.  The higher impedance of the ferrite at the critical frequencies effectively reduces the size of the isolated side's dipole leg to just the area between the IC and the ferrite terminals instead of being the entire plane area + length of attached cable.

Thanks Eric

Please also suggest if we can place these ICs adjacent on Top and Bottom side as shown in Image 3. As there is a space constraint and multiple isolators are used we have placed ICs in mirrored configuration on both TOP side and BOTTOM Side so we are concerned about the coupling of magnetic field and switching noises from TOP to BOTTOM Layer or vice versa.

The ADI isolators should have no functionality issues with being placed immediately adjacent to or on opposite sides of each other on the PCB as I mentioned in my first response.

That being said, the EMI performance regarding radiated emissions will be impacted by the circuit choices and layout.  Placing the isolators & isolated supplies as you are proposing will constrain your options for layout and will make having a good EMI performing layout/circuit more difficult.   Depending on your emissions requirements and other application details, it may be possible to find a suitable circuit & layout in the direction you're pursuing or it may require more substantial changes to the design architecture and/or requirements/specifications.

This is a challenging system design problem with many interacting facets.  Using a pubic forum such as EZ is probably not the most productive method for addressing these issues in a proprietary design.   Utilizing one of the other more private support channels available at https://www.analog.com/en/support.html can offer additional assistance that is not possible in this public forum.

Eric