ADuM342E: About connect the input and output pins to SDIO pin of AD9266

Hello Tomorhiro,

   Using the ADuM342 as proposed for the bi-directional SDIO pin is going to have issues because there needs to be a way for the VOC pin's driver to be disabled to allow the SDIO pin to drive the net when SDIO is an output.   This functionality could be achieved by using VOD to drive a tri-state buffer between VOC and the SDIO-VIB net.  The FPGA could then use VID to control the VOC driver to be active when the FPGA is writing to SDIO and disable / disconnect the VOC driver when the FPGA is reading data from SDIO.

  Another option would be to use a bidirectional isolator such as the MAX14850 or the newer ADuM1252.   The MAX14850 has the benefit of additional unidirectional channels which could be used for the SCLK and CSB lines, however, a combination of the ADuM342 + ADuM1252 would solve this as well.

Eric

ps -  I'm not an expert on the AD9266, but my reading of the datasheet suggests that there are a number of other pins which need to be connected between the AD9266 and the FPGA.   My understanding of the AD9266's datasheet is that the SPI port being isolated is used for configuration/control of the ADC and that these other pins provide the key functionality of clocking the ADC and reading the acquired data.   

Are you also isolating these pins?  If so, perhaps it would be beneficial to look at the isolation needs from a system perspective.  If you're not isolating the other pins, then that raises other questions...

Hello Tomorhiro,

   Using the ADuM342 as proposed for the bi-directional SDIO pin is going to have issues because there needs to be a way for the VOC pin's driver to be disabled to allow the SDIO pin to drive the net when SDIO is an output.   This functionality could be achieved by using VOD to drive a tri-state buffer between VOC and the SDIO-VIB net.  The FPGA could then use VID to control the VOC driver to be active when the FPGA is writing to SDIO and disable / disconnect the VOC driver when the FPGA is reading data from SDIO.

  Another option would be to use a bidirectional isolator such as the MAX14850 or the newer ADuM1252.   The MAX14850 has the benefit of additional unidirectional channels which could be used for the SCLK and CSB lines, however, a combination of the ADuM342 + ADuM1252 would solve this as well.

Eric

ps -  I'm not an expert on the AD9266, but my reading of the datasheet suggests that there are a number of other pins which need to be connected between the AD9266 and the FPGA.   My understanding of the AD9266's datasheet is that the SPI port being isolated is used for configuration/control of the ADC and that these other pins provide the key functionality of clocking the ADC and reading the acquired data.   

Are you also isolating these pins?  If so, perhaps it would be beneficial to look at the isolation needs from a system perspective.  If you're not isolating the other pins, then that raises other questions...

as a postscript/reflection - note that the ADuM1252 has an I2C specific feature which causes it to disconnect when it detects a "stuck bus" condition.  A stuck bus is defined as being when either channel remains "low" for an extended time frame in violation of the I2C standard.  The ADuM1252 declares the bus to be stuck when either SDA1 or SCL1 remain low for more than 102ms (typ).  Provided that the SDIO pin never is low longer than 102ms (typ), the isolator will remain connected.  If there is the potential SDIO could remain low this long, than the ADuM1250 may be the better alternative.

The MAX14850 doesn't detect the I2C stuck bus condition and so this isn't a concern for it.

Hi Eric-san,

Thank you for your description.

I understood very well.

The customer wants to use isolator at simple so I will resarch other ADC.

Best Regards,

Tomo