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Are MAX96715 and MAX9288 compatible?

Thread Summary

The user is experiencing issues with DLOCKED, VLOCKED, and HLOCKED not locking on the MAX9288 Deserializer Board when using a YUV422 format camera with the MAX96715 Serializer. The final answer suggests checking the HSYNC/DE crossbar settings for potential configuration issues.
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Category: Hardware
Product Number: MAX9288

Using (1) MAX9296A Deserializer Board below, I can capture the image. However, if I use the (2) MAX9288 Deserializer Board, LOCKED is normal, but DLOCKED, VLOCKED, and HLOCKED don't lock. I searched on EngineerZone and found content about MAX96705.

(1) YUV422 format camera with MAX96715 Serializer -> MAX9296A Deserializer Board -> MIPI 1-lane Grabber

(2) YUV422 format camera with MAX96715 Serializer -> MAX9288 Deserializer Board -> MIPI 1-lane Grabber

I tried following it, but it didn't improve. What should I check first?

Is the MAX96705 compatible with the MAX9288? - Documents - Interface and Isolation - EngineerZone

[REGISTER_INIT]
// x80 ;Ser Device addr
// x90 ;Des Device addr
DEVADR 0x80 // SER_96715
 x04 x43 // SEREN[7] 'b0: Disable serialization, CLINKEN[6] 'b1: Enable configuration link

DEVADR x90 // Des 9288
 x02 x0F // AUDIOEN[4] 'b0: I2S Disable TDM channel.
 x08 x20 // HVSRC[4:3] 'b00: D18/D19 assigned to HS/VS
 x09 x40 // AUTOPPL[6] 'b1: Automatic pixel count enabled
 x15 x70 // HVTREN[6] 'b1: Enable HS/VS tracking, DETREN[5] 'b1: Enable DE tracking, HVTRMODE[4] 'b1: Partial and full periodic
 x16 xDA // HIGHIMM[7] 'b1: High-immunity reverse control
 x60 x13 // INPUTBW[5] 'b0: YUV422-8b/10b uses muxed mode, DATATYPE[3:0] 'b0011: CSI-2 output uses YUV 422 8-bit
 x65 x47 // DESEL[6] 'b1: HS input is the DE source, DATALANEN[5:4] 'b00: Data lane D0 enabled
 x95 x80 // PD_HDCP[7] 'b1: Power down HDCP circuits

DEVADR 0x80 // SER_96715
 x07 x84 // DBL[7] 'b1: Double-input mode, HIBW[6]0 BWS[5]0 ES[4]0 RSVD[3]0 HVEN[2] 'b1: Enable HS/VS encoding, RSVD[1]0 PXL_CRC[0] 'b0: Serial data uses 1-bit parity 
 x43 x1D // GEN_HS[4] 'b1: Enable VS output generation, GEN_DE[3] 'b1: Enable DE output generation, VS_TRIG[2] 'b1: VS trigger uses rising edge
 x4D xC0 // HIGHIMM[7] 'b1: Use high-immunity mode
 x66 x69 // DE_EN[3] 'b1: Enable separate processing of HS and DE signals, CXSEL[0] 'b1: Coax cable connected to noninverting output
 x67 xC4 // AUTO_CLINK[5] 'b0: Enable configuration link, DBL_ALIGN_TO[2:0] 'b100: Align at each rising edge of HS
 x04 x83 // SEREN[7] 'b1: Enable serialization, CLINKEN[6] 'b0: Disable configuration link

DELAY 100

DEVADR x90 // Des 9288
 i2cr x79 // APPLERR[4] 'b1: Pixels-per-line error detected, DLOCKED[2] 'b0: DE tracking not locked, VLOCKED[1] 'b0 HLOCKED[0] 'b0