High RF Emissions exceeding DO-160G Limits

Hi Thorsten,

I apologize for the late response, but we are working on your question.

If possible, could you please share the schematic and layout of the RS-232 circuit?

Tkanks for your patience,

Andrea

Hello Andrea, 

Thanks for looking into this. 

Unfortunately, I cannot share schematic and layout at this time. 

Thorsten

I would like to add that during my investigations, I saw that the data-lines show the same noise pattern (in the frequency domain), when directly measured with an Oscilloscope Probe (Data-Lines were in steady-state during that measurement). 

I also have noticed that other chips often require ferrites on both the isolated output voltage and the isolated ground. 

Which leads me to the following question: Would it help to put ferrites between the VISO and GNDISO pins and the connection-points of the Capacitors of the charge pumps? Currently I'm suspecting that noise from the VISO pin is coupling into the supply of the RS232 through this way. 

Unfortunately, I don't have any means of testing this, since the traces are too densely packed and I have no chance of making the necessary modifications on it. 

Hi Thorsten,

I agree with you that a noise source can be the isoPower. Assuming this is true, then we need to optimize the Common Mode filtering. To do that, I would suggest:

• Add stitching caps across the barrier to provide a low impedance path for high frequencies. For the stitching caps to be effective the SRF needs to be above the frequency to be filtered.  I would like to suggest to add both a capacitor formed by the PCB layers (that will have very low L and so approaches an ideal cap, but it just is very low valued) and also a discrete cap to get enough C to be effective at lower frequencies.

• Minimize the total area of all conductors on the isolated side of the transceiver. The idea is to shrink the isolated side part placement and CU area to be as small as possible and then add CM filtering to anything leaving this small area, such as the RS-232 signals. This obviously does not apply to the stitching cap created on the PCB layers where you have to enlarge the area to have more capacity, but it does apply to the copper traces leading to the capacitors, which must therefore be as close as possible.

• Make sure to have a good supply decoupling layout. This means the Viso decoupling capacitor should have high SRF – well above the frequencies where you are having issues. You also need to pay attention to the layout regarding the decoupling loop. With the supply pins on opposite ends of the IC (pin 11 and 20), you have to put the cap on one end and use vias to drop to another layer to reach the Viso/return on the other side. You should use multiple vias at both ends and make the lower layer “trace” more of a plane (to minimize parasitic L).  I’d incorporate this plane as part of the stitching cap structure as well which will allow it to be larger.  This has the double benefits of reducing the series L of the decoupling loop as well as increasing the stitching cap value.

• If this is not enough, there is also the possibility to work in the logic side by adding a CM filter on that side and reducing the non-stitching cap area.  Note that this CM filter needs to handle the power for the IC as well as the signals.  The signal filter and power filter parts will likely need to be different due to the current requirements.

• There is also the possibility to increase the filter order by adding another stitching cap around the output(s) of the series CM filters. Then, it is possible to add additional series CM filter as well.  Note that this 2nd level of stitching cap/CM filter is usually more effective at lower frequency conducted emissions due to the parasitics which will limit the benefits.

Hopefully, improving the stitching cap realization, shrinking the area before the CM filter, ensuring a good supply decouping for Viso and adding the CM filter will be enough!

Please feel free to ask if you have any questions or concerns.

Kind Regards,

Andrea