Question about power sequence of ADG3123

Question

Hello, This is Kwonjoon Lee from South Korea. I would like to ask about power sequence of ADG3123. 
 
 (Detailed Situation) 
 1. VSS of ADG3123 is connected to an output pin of the analog (unity gain feedback) buffer circuit. 2. The analog buffer circuit is fully turned off before start-up of ADG3123. 3. Target voltage of VSS of ADG3123 is a negative voltage. 
 (Detailed Question) 
 1. In the case of start-up of ADG3123, I would like to ask if VDDB can be firstly turned on (a few tens of ms) before turning on VSS (negative voltage). 
 
 Best regards, Kwonjoon Lee

Christian · Accepted Answer

Hi KwonjoonLee , 
 For the ADG3123, it is crucial to follow the recommended power sequence to ensure proper operation and avoid potential damage. According to the datasheet, the VDDB must always be greater than or equal to the VDDA, and the voltage between the VDDB and VSS should not exceed 35 V. 
 In your specific case, where VDDB is turned on before VSS, it is generally acceptable as long as the following conditions are met: 
 
 VDDB is greater than or equal to VDDA . 
 The voltage difference between VDDB and VSS does not exceed 35V . 
 
 Given that VDDB is turned on a few tens of milliseconds before VSS, this should be fine as long as the above conditions are maintained. Best regards, Christian)

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Question about power sequence of ADG3123