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Based on the iCoupler® and isoPower® chip scale transformer technology, the ADM3260 is a hot swappable digital and power isolator with two nonlatching...
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ADM3260: SDA side 2 stays high while SDA side 1 goes low



		

			

									
					    Julian1234
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Sep 4, 2024 
				
			
			
		
    

				
		
    
		    		    
		    
		    		      		            		        
    Category: Hardware
    
    		        		            		    
    Product Number:  ADM3260 
    
    		        		    		    	
			
    Hi!
    

    I am using an ADM3260ARSZ. On side 2 there is a STM32F439GV (main). On side 1 there is a BQ3050 (device). I am trying to initiate a communication between those two. In the following picture you see the main(SCL: Blue + SDA: Red) transmitting an I2C request to the device (SCL: Green + SDA: Yellow). As you can see, the mainsends the 8 address bits and the deviceacknowledge the request by pulling sda (yellow) low. Nevertheless the ADM3260 ignores the acknowledge and the main's sda stay high (red).
    

     
    

    For me it looks like the ADM3260 only checks the SDA input on the SCL's falling edge!? As you can see after the next SCL falling edge, when the SDA is indeed pulled low.
    

    How could this be? The BQ3050 can not acknowledge faster. And probably many other I2C components are not fast enough either. How can I solve this problem?
    

    
									
			        
		
    

				
						
        

    
    Tags: 
                                            
                 hardware
                
                                                    
                 Digital Isolation Technology
                
                                                    
                 i2c
                
                                                    
                 adm3260
                
                                                    
                 I<sup>2</sup>C Isolators
                
                                
            
    
    
    

		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    


	
    
		
	
    















    
	
    
	
    
					



			








	
	
	
	



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      •  Analog Employees  
      
            
			                            
                                                                                                                        
            
				
			
            
					
      
	
      

		
		
      
					
      Hi Julian,
      

         I suspect that the SDA voltage during the ACK period on the ADM3260 side 1/device SDA node is low, but not low enough for the ADM3260 to recognize it and so the ADM3260 is keeping the side 2 SDA high.  The device is pulling SDA1 low fast enough with plenty of time remaining for the ADM3260 to detect and drive the other side low before the rising edge of the SCL.  Also, I'm pretty sure that the reason the red SDA falls with the clock's falling edge is that the controller having (incorrectly) observed a NACK then pulls SDA low in preparation for generating the Stop condition.
      

         What are the low level voltages at the pins of the ADM3260?
      

      Eric
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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						in reply to ericb
					
									
        
	
        

		
		
        
					
        Hey Eric,
        

        Thanks for your reply!
        

        I measured the following voltages of the SDA lines. The positions are marked in the picture.
        

        


        
Where
1
2
3
4
5 (max)
6
7
8

        

        
Side 2 / Main / Red
3.30 V
0.15 V
3.30 V
0.15 V
3.30 V
3.30 V
0.15 V
3.30 V

        

        
Side 1 / Device / Yellow
3.28 V
0.48 V
3.29 V
0.48 V
3.11 V
0.41 V
0.46 V
3.29 V

        
        

        

         
        

        

        1. For my understanding: The ADM3260 "ignores" the I2C protocol, correct? So It just transmits the raw signal without interpreting the signal. So the ADM3260 does not know about ACK, address, etc.
        

        

        I suspect that the SDA voltage during the ACK period on the ADM3260 side 1/device SDA node is low, but not low enough for the ADM3260 to recognize it and so the ADM3260 is keeping the side 2 SDA high.
        

        

        2. The SDA voltage of the device is lower during the ACK phase than elsewhere as you can see in my table above (0.41 <-> 0.46 V). I watched this tutorial video about how Analog's I2C isolator works. So maybe you are right, the voltage at 6 needs to be lower, so the isolator redirects the signal from side 1 to 2.
        

        

        But what is the needed voltage? As I understand the datasheet, the voltage at 6 needs to be 50 mV lower than measured at 7? (-> Input/Output Logic Low Level Difference). I will try to increase the pullups a bit more, so the difference might increase enough.
        

        

         
        


        

        Best regards
        

        Julian
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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						in reply to Julian1234
					
									
          
	
          

		
		
          
					
          Indeed, increasing the pullups to 3.3k did the trick...
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
						
						
				
				
		
		
          
			
		
          
	
          

          

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