SPI Polarity Inversion in ADP1031ACPZ-1-R7 Isolation Channel

The ADP1031ACPZ-1-R7 chip has a spi isolation channel, but when I send a signal from the PS side of the ZYNQ chip to control the SPI, the polarity of the SPI's clk and mosi will be inverted, resulting in a communication failure, but using the SPI interface from the PS side of the other chip (which does not have the SPI isolation channel of the ADP1031ACPZ-1-R7 chip) does not cause this problem (this SPI can communicate normally and the polarity is high in the idle state, while the signal coming out of the FPGA through the ADP1031ACPZ is high in the idle state. This problem does not occur (this SPI can communicate normally and the polarity of the level in the idle state is high, while the signal coming out of the FPGA through the ADP1031ACPZ is low in the idle state).