LTC4332 Remote SCLK HIGH between bytes

Question

Hi, 
 I am noticing that the remote SCLK for the LTC4332 is high between bytes. 
 
 While the SCLK frequencies align with the local and remote sides, my slave device requires the clock to be LOW between bytes and bits (essentially the remote SCLK should mimic that of the local). Is there any way around this? 
 
 Thanks

ericb · Accepted Answer

Looking at your SCLK waveforms, it appears that the actual link speed is faster than your local SCLK with the result that the remote SCLK waveforms are asymmetrical in the high/low times. The LTC4332 sets its remote side timing parameters such as the clock low (or high) time or setup and hold times to be compatible with the assumed SCLK speed. Having a much faster link speed than the desired SCLK frequency could result in timing violations. 
 In particular, the LTC4332 does properly respect the configured SPI mode; however, in between words, it can leave the clock in one state for most of the interval and only transition the clock to the idle state just before the next edge per the associated setup/hold timing. I suspect that if you slow the link speed down to be equal or just above your local SCLK frequency, things will work better. 
 That being said, you can configure different SPI modes with modes (0,0) and (0,1) having a low clock in idle. Note that the default for the LTC4332 is mode (0,0), so its already set as you want. The modes are configured individually for each chip select and are set through the control interface by writing to the local SPI device using the nSSC chip select. For more details see the datasheet's pages 15-17. 
 Eric)

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LTC4332 Remote SCLK HIGH between bytes