Gate Low Fault(GL_FAULT) logic using GATE_SENSE pin

Question

Regarding ADuM4177 Gate Low(GL_FAULT) fault logic in datasheet. If gate_sense goes above 12.1V, GS_R goes high, the first AND gate must output low, with a delay, GL_Fault stays low. But during OFF periods, the fault pin goes high in simulation. How to prevent this? Should the schmidt trigger be disabled in that period?

LMartini · Accepted Answer

As represented in the equivalent circuit diagram, the input comparator is enabled or disabled according to the logic level of the DRIVE signal. Regards)

Partner Forums

Partner Libraries

Products Mentioned

Gate Low Fault(GL_FAULT) logic using GATE_SENSE pin