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Gate Low Fault(GL_FAULT) logic using GATE_SENSE pin

Category: Datasheet/Specs
Product Number: ADuM4177

Regarding ADuM4177 Gate Low(GL_FAULT) fault logic in datasheet. If gate_sense goes above 12.1V, GS_R goes high, the first AND gate must output low, with a delay, GL_Fault stays low. But during OFF periods, the fault pin goes high in simulation. How to prevent this? Should the schmidt trigger be disabled in that period?