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Modelling Desat Protection scheme of ADum4146 in LTSpice

Category: Software
Product Number: ADUM4146

Hi, I am trying to model the Desat protection scheme of ADum4146 and similiar isolated SiC MOSFET gate drivers. The waveforms obtained from the test circuit of  the IC by AD on LTSpice is shown as below. But as I try to model it with a current/voltage source, I see a high voltage on Vdesat as the MOSFET is turned off, contrary to the IC waveform where it rises as the MOSFET is on. What corrections should I make in my model to achieve similar results?