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Driver design for SiC MOSFET Full Bridge Inverter with Vds=100V, can not go higher than Vds=50V (SiC MOSFET rated for 650V)

Category: Hardware
Product Number: adum4121

Hello everyone,

I am writing to you in search of help. I've spent a couple of weeks trying to figure out what I'm doing wrong, but I'm still not clear on what I'm doing.

I am working on the design and prototype of a full-bridge inverter and have chosen ADUM4121 as the isolated gate driver and C3M0120065K as the SiC MOSFET (Vds=650V, Id=22A) for the converter. Both manufacturers (Wolfspeed and Analod Devices) recommend them as a matching pair.

Each SiC MOSFET has its driver and unregulated isolated DC-DC source (R15P21503D). Therefore no boot trap is required.

The inverter's DC link is rated at 100V, and the load is a series RL (R=10 Ohms and L=4mH).

The modulation is a unipolar sinusoidal PWM.

I've followed the design of KIT-CRD-8FF65P (650V), which uses the same driver and isolated DC source I use. However, for the new SiC MOSFET, I changed the gate resistor to Rg(on)=10 Ohm and Rg(off)=5 Ohm (Cgs and Rgs are avoided).

The problem is that although the taken example is made for Vds=650V and my design is made for Vdc=100V, when I reach 40V from the DC source (DC link) some high peak currents start to appear at the SiC MOSFET drain (4 times higher than the nominal current), killing my SiC MOSFET devices.

The only solution that worked was to increase the Rg(on,off) from 10 ohms to 50 Ohms, which is too high for a common application.

Simulations work perfectly, but the prototype does not.

Is there something I've missed?
Is 50 ohm too high as gate resistance Rg?
The schematic is attached, and I can attach oscilloscope screens if needed.

Thank you very much for your support!

  • Hi PabloGuicharrousse,

    How much dead time are you applying on the PWM signals? Did you try to increase the dead time to rule-out possible shoot through issues?

    An oscilloscope capture of the over current event and PWM signals can help to debug the issue.

    Regards,
    Luca
      

  • Hello Luca,

    Thanks for your reply!

    I increased the dead time (400ns with 20kHz carrier frequency for the PWM), but the circuit has the same limitation.

    As soon as I get the oscilloscope images, I'll be back.

    Kind regards,

    Pablo

  • Hi Luca,

    I'm back on my Full-Bridge Inverter, and for more accuracy regarding my problem, I have taken screenshots for the Double Pulse Test. Vdd=70[V].


    Considering the previous circuit:

    • Device Under Test is the U2
    • U1 is permanently off.
    • U3 is permanently on.
    • U4 is permanently off.

    Some strong oscillations appear during the turn-on and turn-off drain current.

    The turn-on ID current does not even show clear behaviour.

    I am trying to find some ideas on how to suppress them. I think that it could be related to capacitors C16 and C15, but not sure.

    Do you have any idea on what could cause that oscilations when using ADUM4121?

    Thanks for your help!

    Double Pulse Test (yellow Vds, blue Id)

    Turn-on (yellow Vds, blue Id)

    Turn-off (yellow Vds, blue Id)

    Kind regards,

    Pablo