KCC's Quizzes AQQ304 - A pure logic
1. Quote of the month: "I am not lazy, I'm just in energy-saving mode" - unknown
2. Quiz AQQ304 about finding a pure logic puzzle
Mike is looking at Anne, but Anne is looking at Paul.
Mike is married, but Paul is not.
Question:
Is a married
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September Monthly Blog Quiz! Read the blog, take the quiz, and you could win a gift card
Quiz: How Well Do You Know Adaptive Power Switching?
Is your I/O module overheating? The AD74416H's Adaptive Power Switching (APS) can cut heat dissipation by up to 40% — but how well do you really understand how it works?
Read the blog first: Cooling
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ADN4624
Recommended for New Designs
The ADN4622/ADN4624 are quad-channel, signal isolated, low-voltage differential signaling (LVDS) buffers that operate at up to 2.5 Gbps with very low jitter...
Datasheet
ADN4624 on Analog.com
ADN4620
Recommended for New Designs
The ADN4620/ADN4621 are dual-channel, signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 2.5 Gbps with very low jitter...
Datasheet
ADN4620 on Analog.com
ADN4650
Production
The ADN4650/ADN4651/ADN46521 are signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 600 Mbps with very low jitter...
Datasheet
ADN4650 on Analog.com
Hi,
(I am a LVDS newbie) I am eyeing medical LVDS isolators (Creepage and clearance > 8.3mm) to perform parallel data transimissions (Probably 100MHz per LVDS line, I am after EMC benefits, not so much speeds) between two FPGAs isolated from one another. One of my FPGAs is limited to have 1.8V differential, HP or high performance IOs, hence I am limited to LVDS18.
Looking at the "ADN462X" and "ADN465X" LVDS isolators, I can't seem to understand the relationship between the supply and the IO supply voltages. For example, ADN4624 has ONLY VDD1 and VDD2 that can take separate 1.8V supply voltages for each of the isolated sides, but then if I feed LVDS1V8 signals to the ADN4624, do I get LVDS1V8 as an output? the data sheet recommends IO signal voltages to be 3 - 3.6V. It gets complicated when we discuss the ADN4620, which not only has VDD1 and VDD2, but also VIO1 and VIO2. VIO1 and VIO2 both got a recommended voltages of 3.3V, does this mean I can only perform LVDS3V3? if I do supply the 3.3V VIO voltages for the ADN4620 and I use LVDS1V8 in the input stage, do I get LVDS1.8 as an output? I just want a solution to provide and receive LVDS1V8 on either ends of the isolation chips.
Many thanks.
Hi,
Thanks for reaching out!
LVDS levels are not dependent on the supply voltage. The common mode voltage of the LVDS input/output is always around 1.2V, disregarding of the supply voltage. So every compliant LVDS input and output will be compatible to that common mode voltage, no matter what is the supply voltage.
Would you give me any more high level detail about your medical application? what is this used for? what's the FPGA you are using?
Thanks again and Kind Regards,
Riccardo
Given that my prototype has the ADN4650, this means I can connect the orange labels straight into differential 1V8 tolerant HP IOs since what is considered here is the common mode voltage which is 1V2, not the actual supply voltage of 2V5 (The ADN4650 has got 2V5 LDO works from the 3V3 supply)?
Hi,
Yes, I confirm. What's the FPGA you are using? is it an LVDS compliant input?
Kind Regards,
Riccardo
Its the new Kria 24 SOM by AMD, the following is the LVDS spec 