Two LTC4313-2s Connection

Hello Hiroyuki,

   In general, this use case scenario should be possible.  Some things to check / confirm include:

* The pull-up resistor values need to be sized in order to assure the rise time of the associated bus segment is at least 0.4V/us and that the maximum bus current is less than 4mA.  This sizing will depend on the effective capacitance of associated bus segment which includes the device pin capacitances plus the bus (or cable) parasitic capacitance to GND.  See Equations 1 and 2 on page 9 of the datasheet. 

* The input-output offset voltage of the cascade plus the V_OL(max) of the FPGA and the Temp Sensor IC will remain below the V_IL of the Temp Sensor IC and FPGA respectively.  See pages 9 and 15 of the datasheet.  Note that Equation 3 is applicable when the driven low input is >=200mV.   If the driven input low is below 200mV, use the typical performance curves V_OS vs I_BUS typical performance curves on pg 4. 

* It is not specified how close the PCBs are located or how they're connected together.  If they are "far" apart and connected with a cable, then the cable conductor configuration / construction may be important to consider.  A longer cable can have increased potential for cross talk between SDA and SCL.  If this is the case, then cable constructions with different internal twisted pair pitches and placing the SCL and SDA in different twisted pairs with GND could minimize the cross-talk.

*it is not specified if the bus pull-up voltage is the same as the V_CC supply or if they are different.  The copied datasheet figure shows them the same, but if they are not, you will want to make sure that the bus pull-up voltage is at least 0.9*V_CC so that the rise time accelerators do not over drive the SDA/SCL bus segments.  See pg 8 and 9 of the datasheet.

Eric

Hello Eric,

Actually the customer is facing the error communication between FPGA and Temp IC. If two LTC4313-2 is replaced by LTC4313-3, is there a possibility that the error will be improved ?

Regards,

Hiroyuki

I would not expect simply swapping in some LTC4313-3's for the existing LTC4313-2's will resolve communications errors.  It might if the cause of the communications error is due to the rise time accelerators - the LTC4313-3 removes the accelerators present in the LTC4313-2.

The cause of the communications error could be due to different things and its likely that it would be related to the items above I suggested checking/confirming. 

Note that this isn't an exhaustive list and that there are other potential sources of issues - for example, most FPGA's have different configuration settings for their output driver stage and the configuration tool may allow setting I2C pins to have a push-pull driver output instead of an open-drain.  Using a push-pull driver can cause issues with the bus-buffer being unable to follow the very fast rising edge generated by the push-pull driver.  This can result in the buffer fighting with the driver and creating a non-monotonic rising edge which could cause false transitions to be detected. 

Eric

Hello Eric,

I also have a question regarding the content related to this case.
I am trying to use the LTC4313-1 in a circuit similar to that of Hiroyuki's, but the waveform is distorted at the rising timing of the SCL1 and SDA1 signals as shown in the attached image.
Is there any possible cause for this?
The FPGA is Cyclone10LP and the I/Ostandard is 3.3V LVCMOS.

Hello Akrsssss,

   This rising edge of this waveform is what I'd expect to see when the bus buffer is being driven by a push-pull output stage instead of an open-drain with a typically sized R pull-up. 

I'm not familiar with your FPGA; however, the I/O configuration of 3.3V LVCMOS sounds like is probably a push-pull driver.  You likely need to change it to open drain or similar.  Perhaps there's an actual I2C option which sets the driver as open-drain and enables the receiver/input on the pin to make it bidirectional.

Eric

Hello Eric,

Thank you for your response.
As far as I can tell, there doesn't seem to be a way to set up an open drain in cyclone10LP, but is there any other way to prevent this?

Hi Akrsssss,

  Our bus buffers are designed to work with standard I2C bus drivers and so you'll need to properly configure your FPGA's I/O pins to follow the I2C specification for open-drain drivers.  

  I believe that this is possible and suggest you follow up with your FPGA's manufacturer for guidance on how to make this configuration in your design. 

Eric