Recommended Digital SPI Isolator for 2xMAX1230 ADCs

Hello Andreas,

   Simply looking at the I/O channel configuration, the ADuM3152 might be a candidate since it has 4 high-speed isolation channels for CLK, data in, data out and a chip select as well as 1 forward and 2 reverse auxiliary channels.  Thus you could use the intended chip select and the forward aux channel for selecting the two ADCs and the 2 reverse channels for their end-of-conversion signal.  

   There are, however, some timing considerations which need to be reviewed in the context of your application's requirements.  Depending on your application this isolator may or may not be suitable.

   First, the aux channels are lower speed, sampled and multiplexed so there is some jitter depending on when the input changes relative to the sampling point of that channel.  Because of the potential for skew between the aux channel and the CLK channel, you'll need extra setup time when selecting that device, which will reduce your data throughput and potential limit the number of channels and/or the sampling rate.  

   Next, reading through the MAX1230 datasheet, it appears that there are 4 different clock modes.   Two modes require an nCNVST signal to trigger the conversion start and two use an edge on SCL to trigger the conversion.  Since you didn't mention the need for isolating the nCNVST signals, presumably you're not using those modes.  For the SCL triggered conversions only one uses the nEOC signal, so based on your I/O description, I'm assuming you're planning on using the MAX1230's clock mode 10 which should work OK assuming the timing on receiving the nEOC is not critical.   Similar to the select on the aux channel mentioned above, this will also have timing jitter which will impact the sampling rate since you'll likely need to include this in the sampling period timing calculation.

  If these timing limitations are not OK for your application, I would suggest looking at using 2x ADuM340E.  This offers 4x high speed channels with very fast and well controlled timing, both channel to channel and part to part.  One ADuM340E could handle the 4x forward signals and the other the 3x return.  Depending on your isolation requirements, there are two package options for a VISO of either 5.7kVrms or 3kVrms.  

Eric

Hello Andreas,

   Simply looking at the I/O channel configuration, the ADuM3152 might be a candidate since it has 4 high-speed isolation channels for CLK, data in, data out and a chip select as well as 1 forward and 2 reverse auxiliary channels.  Thus you could use the intended chip select and the forward aux channel for selecting the two ADCs and the 2 reverse channels for their end-of-conversion signal.  

   There are, however, some timing considerations which need to be reviewed in the context of your application's requirements.  Depending on your application this isolator may or may not be suitable.

   First, the aux channels are lower speed, sampled and multiplexed so there is some jitter depending on when the input changes relative to the sampling point of that channel.  Because of the potential for skew between the aux channel and the CLK channel, you'll need extra setup time when selecting that device, which will reduce your data throughput and potential limit the number of channels and/or the sampling rate.  

   Next, reading through the MAX1230 datasheet, it appears that there are 4 different clock modes.   Two modes require an nCNVST signal to trigger the conversion start and two use an edge on SCL to trigger the conversion.  Since you didn't mention the need for isolating the nCNVST signals, presumably you're not using those modes.  For the SCL triggered conversions only one uses the nEOC signal, so based on your I/O description, I'm assuming you're planning on using the MAX1230's clock mode 10 which should work OK assuming the timing on receiving the nEOC is not critical.   Similar to the select on the aux channel mentioned above, this will also have timing jitter which will impact the sampling rate since you'll likely need to include this in the sampling period timing calculation.

  If these timing limitations are not OK for your application, I would suggest looking at using 2x ADuM340E.  This offers 4x high speed channels with very fast and well controlled timing, both channel to channel and part to part.  One ADuM340E could handle the 4x forward signals and the other the 3x return.  Depending on your isolation requirements, there are two package options for a VISO of either 5.7kVrms or 3kVrms.  

Eric

Jason's comments about the MISO are good and while focusing on the timing aspects, I forgot about the potential MISO contention.   Using 2x ADuM341s would probably be a better choice.  Note that the nEOC's will need to be active even when there isn't a chip select, so put the MISO channel on the single return of the ADuM341E and the nEOC's on the other ADuM341's return channels.

Hello Eric,

unbelievable how quickly I get detailed feedback and support here, very much appreciating you guys time and effort!

What you are writing is all correct:
As we do need 16 differential channels, using the nCNVST signal is not an option as this would reduce the channel count.
And as we plan to use the internal reference, clock mode 10 with the nEOC signal is the way to go, indeed.

While likely not the full sampling rate bandwidth will be required, we would prefer to not artificial limit this by the isolator at this point.
2x ADuM340E therefore seems the better option.

Another option I would see is using 1x ADUM3154 (using 2 of the 4 supported SPI slaves) and then 1x MAX12930 for the 2 additional required nEOC back channels.
This might be a bit more expensive (as 2 SPI slaves stay unused), but might be simpler in regards to MISO contention?

Best regards
Andreas

Hi Andreas,

   Since your application doesn't have other devices sharing the return data connection between the isolator and controller, you don't need to worry about the contention issue Jason mentioned.  I supposed you could still implement the circuit to make that line go high-Z to be fully SPI compliant, but why add the cost and complexity...

   Your idea about the ADuM3154 + MAX12930 could also work; however, you still need to account for the setup time for the chip selects I mentioned above. 

Eric 

Thanks again, Eric!

Just to be sure I got all correctly, I've created two example schematics with the SPI parts only.

First variant with 1xADuM341E and 1xADuM342E:

And second variant with variant with 1xADuM3154 and 1xMAX12930:

Without MISO contention as not needed like discussed, these should both work like drawn above, correct?

Regarding the required setup time for the chip selects you mentioned, I would expect that you have this in both of these variants:
With the first one you need to disable one CS plus enable the other and with the second you need to set the right CS_BIT and enable MSS or do I miss something here?

Would you consider one of the two variants better/cleaner than the other?
Which one would you choose? :-)

Best regards and thanks again for your efforts
Andreas

Quickly looking over your circuits, I'm not seeing any obvious errors and would expect either should work.

In terms of what I'd suggest, I'm going to stick with my original suggestion of 2x ADuM340Es.  While the ADuM3154 has good SPI performance and should be good enough, the chip select is slightly more complicated.  Using the ADu34xE simplifies the chip select and gives a bit better timing performance which will let you maximum your data throughput for the most samples per second.  Using an ADuM341E and an ADuM342E will give the same performance as 2x ADuM340E, but the ADuM340E gives you BOM simplification and larger order quantities which may help get you to a lower price break,

Eric

That makes totally sense what you're writing, Eric!

2x ADuM340E seems indeed the best/simplest and most cost effective option for this use case:

Again, thanks a lot for all your efforts, both Eric and Jason, this is much appreciated!

Andreas