Sometimes MAX14850AEE+ has a large propagation delay from I/OB1 to I/OA1

Maybe sometimes I/OB1 miss rising edge and DC levels refresh is occured between I/OB1  and I/OA1 after ~7us. How often DC levels refresh is occured between I/OB1 and I/OA1?

Hello,

   Regarding the propagation delay, this is puzzling and will need some investigation.  To start with, how many systems have you made and does this happen in all or some of them?  That is, is this a single prototype or are there multiple units which have been built?

   In terms of your second question, what does the dc supply rail at the part look like?  The output driver of I/OB1 is an open-drain pull-down transistor so the rising edge is generated by the pull-up resistor and the dc supply rail.  The switching modulation on the waveform suggests a potential issue with the dc supply, perhaps insufficient decoupling or large impedance or ...

Eric  

ps - while I don't see the connection right now, its possible that the two issues are related -> looking at the waveforms in the 1st figure, the disturbance spikes in the green/yellow high levels when the yellow/green transitions suggests issues with the supply...

Thank you for response!

ericb said:

That is, is this a single prototype or are there multiple units which have been built?

Tomorrow I will have another board with same isolator. I will try reproduce it using another board.

ericb said:

In terms of your second question, what does the dc supply rail at the part look like?

MAX14850 decoupling capacitors are C0402C104K4RAC (X7R) and I have next PCB layout:

ericb said:

The output driver of I/OB1 is an open-drain pull-down transistor so the rising edge is generated by the pull-up resistor and the dc supply rail.

To exclude slow slew rate on the I/OB1 I use FPGA 'high' and 'low' levels during I2C transitions(my I2C chip allows it):

ericb said:

when the yellow/green transitions suggests issues with the supply...

Yellow and green probes are far from MAX14850. Tomorrow I will capture scopes near I/OA1 and I/OA2 pins.

ericb said:

That is, is this a single prototype or are there multiple units which have been built?

I have reproduce this error on the another board. On the another board MAX14850 has been ordered from another supplier. So error is reproduced with original MAX14850.

ericb said:

In terms of your second question, what does the dc supply rail at the part look like?

In last post I have decribed power supply for MAX14850. Is it ok?

I have increased I2C SCL frequency to reproduce problem easier.

I have captured VCCA(between C54 terminals) using active probe with short ground when issue is occured. It is ok:

CH4(pink) - I/OB1 signal
CH2(green) - I/OA1 signal
CH3(purple) - VCCA

And also I have captured I/OA1 near chip using active probe with short ground when issue is occured. I/OA1 has "decoupling" problems:

CH4(pink) - I/OB1 signal
CH2(green) - I/OA1 signal

Also I have captured VCCB(between C51 terminals) using active probe with short ground when issue is occured. It is ok:

CH4(pink) - I/OB1 signal
CH2(green) - I/OA1 signal
CH3(purple) - VCCB

I don't see problems with PCB power supply.

Your figure showing how things are connected was helpful and I think that the cross-talk of the SPI clock appearing on the SDA is due to the ribbon cable and not modulation of the dc supply due to poor decoupling as I initially thought.  In your cartoon, the signals are adjacent and during the rising edge of SDA, the node will be relatively high-impedance and so more susceptible to the interference from the SPI clock.

In terms of the missing / delayed pulse, does it only happen to the I/O channel 1 (SDA) or does the other channel also have similar problems?