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About signal isolation of ADN4654 VBO HS

Category: Hardware
Product Number: ADN4654

Hi ADI team:

I am using AND4654 chip, I want to go to isolate the 4K 60HZ V-BY-ONE signal, but after using ADN4654,

I found no image output after connecting the VBO connector to a 4K monitor,

I would like to ask if the ADN4654 can isolate the V-BY-ONE signal?

If isolation with ADN4654 is not possible, are there any other solutions?

Editorial content
[edited by: weialexia at 12:37 AM (GMT -5) on 9 Nov 2023]
  • Hello,

    What is the voltage level range and data rate of V-BY-ONE signals? The ADN4624 is a fresh new release which can support up to 2.5Gbps per lane and can be used both for LVDS and CML signals.

    We have a working reference design for the isolation of 1080p HDMI signals if it is of any interest for you.

    Please reach out to me directly for further info: 



  • Hi, thanks for your reply!
    I measured a pair of differential signal voltages of VBO is about 1.15V and 1.21V, this is the voltage before isolation, after isolation their voltages changed to 2.2V and 0.175V, this is not normal, I am using 4K60HZ, according to the protocol of the VBO shows that his rate should be 600Mbps per channel, a total of 8 channels, so I am using four ADN4654, like the drawing above.
    VBO has two consoles called HTPDN and LOCKN, HTPDN detects that the cable is inserted and can be pulled down normally indicating that the hot-plug detection is successful, but the LOCKN is not pulled down normally indicating that the CDR technology is not acquiring the clock information and the isolation is leading to a signal communication problem. Please provide me some advice on what to do!

  • Hi,

    Usually when indicating the voltage of a differential pair we indicate: common mode values and differential values. What are these values for V-by-one protocol?

    If LOCKN is not asserted this could mean a number of things:

    - the conversion network is not correcly designed. The conversion network is dependent on the protocol, that's the reason why I am asking about V-by-one signals levels. It's purpose is to convert V-by-one signals to LVDS levels accepted by the isolator. You can attach the reference to the protocol if you like.

    - there is a SI issue, in that case we must have a look at your layout. But this is not what I am expecting from a 600MBps signal.

    - Since you are using multiple parts, what is the maximum part to part skew accepted by the protocol and your system?

    - What happens to the lines when they are not commuting/ the system is in power-saving mode? are they in a predefined state? is this matching with the high level fail safe of ADN4654?

    Having an answer to all these question would be the first step to understand how to fix your problem.



  • Hello.
    I understand from the internet that the common mode voltage of the VBO is between 0.5V and 1.5V, while the differential mode voltage should be between 0.4V and 1.2V. Not sure he is accurate as it is not mentioned inside the official datasheet.
    I did the equal length treatment in the PCB layout, and it can communicate normally when no isolation chip is used, as shown in the picture, so I think it might not be the PCB or the system mode that is causing the problem
    I found a problem, 600Mbps is the minimum rate of each channel when it outputs a 4K60HZ screen, according to the signal quality and color depth VBO will adjust the rate of each channel, this rate after calculating the formula to calculate the highest can reach 2.22Gbps, this is also I doubt it will be the rate of the chip does not satisfy the VBO signals, so it leads to the problem, I might consider sourcing an ADN4620 to test.
    I look forward to receiving your updated answer!

  • Hello,

    If input common mode and differential voltage are within the above mentioned ranges, they are compatible with the isolator Slight smile

    Is the VBO differential pair AC or DC Coupled? this might have an impact on the design of the input conversion network, if needed.

    Does the VBO protocol make use of EI (Electrical Idle)? in that case an external fail safe network might be needed.

    If you could monitor with an oscilloscope an on going communication and attach some screenshots would be very helpful.

    Length matching can get rid of board asymmetries. But for sure does not account for the part to part skew of the single components. In case of the ADN462x family will be typically around 150ps. That means that your inter pair skews won't reach lower values even if perfect ideal matching is applied. Is 150ps of inter pair skew acceptable for the VBO protocol?

    What is there at the receiver end? an FPGA? they could have deskew IPs available if that is a problem.

    Why are you considering the ADN4620 and not the ADN4624? the ADN4624 has 4 channel integrated in the same package.

    I confirm that the ADN4654 is not enough for isolating 2.22Gbps, for that speed you need the ADN4620 or ADN4624 which can go up to 2.5Gbps.

    Looking forward for your answer.

    Thanks and Kind Regards,