MAX96717F
Recommended for New Designs
The MAX96717F GMSLâ„¢ serializer receives video on a MIPI CSI-2 interface and outputs it on a GMSL2 serial link transceiver. Simultaneously, it sends and...
Datasheet
MAX96717F on Analog.com
MAX96724F
Recommended for New Designs
The MAX96724/F/R deserializer converts four GMSLâ„¢2/1 inputs to 1, 2, or 4 MIPI D-PHY or C-PHY outputs. The device allows simultaneous transmit bidirectional...
Datasheet
MAX96724F on Analog.com
Hi, I'm trying to interface with GMSL2 solutions[MAX96717F-MAX96724F].
Now, The I2C bus config seems no problem(enable to access, re-address, broadcasts to every devices). However, I'm stuck with MIPI lanes settings.
I have several scenarios need to set to MAX96717F-24F.
Any Ideas for settings to complete these scenarios?
Scenario 1, bring up test : [1x 2-Lane MIPI Camera(Raspi) -> Serializer -> Q-Deserial 1x 4-Lane Port0 -> 2-Lane MIPI SoM ]
Scenario 2 : [1x 4-Lane MIPI Camera -> Serializer -> Q-Deserial 1x 4-Lane Port0 -> 4-Lane MIPI SoM]
Scenario 3 : Full (4x of Scenario 2) [4x 4-Lane MIPI Camera -> 4x Serializer -> Q-Deserial 1x 4-Lane Port0 -> 4-Lane MIPI SoM]
About scenario 2 & 3, I guess that it can easily set to MIPI profile 1. However, due to the hardware limitation, it can't be test right now till the new board finish.
So, I'm focusing on scenario 1 Using Raspi-camera V2.
I'm using [CSI configuration tool, GMSL GUI 1.4.2] to generate scripts and use it as the reference. -> SoM seems to find the camera using I2C, but no video output(black) while streaming.
These are the generated one.
/*
# Name: User
# Date: 10/10/2023
# Version: 1.4.2
#
# I2C Address(0x), Register Address(0x), Register Value(0x), Read Modify Write(0x)
#
# THIS DATA FILE, AND ALL INFORMATION CONTAINED THEREIN,
# IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO
# THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
# PURPOSE AND NONINFRINGEMENT.
# IN NO EVENT SHALL ANALOG DEVICES, INC. BE LIABLE FOR ANY CLAIM,
# DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE DATA FILE,
# THE INFORMATION CONTAINED THEREIN, OR ITS USE FOR ANY PURPOSE.
# BEFORE USING THIS DATA FILE IN ANY APPLICATION FOR PRODUCTION OR DEPLOYMENT,
# THE CUSTOMER IS SOLELY RESPONSIBLE FOR TESTING AND VERIFYING
# THE CONTENT OF THIS DATA FILE IN CONNECTION WITH THEIR PRODUCTS AND SYSTEM(S).
# ---------------------------------------------------------------------------------
#
# _____ _____
# /\ | __ \_ _|
# / \ | | | || |
# / /\ \ | | | || |
# / ____ \| |__| || |_
# /_/ \_\_____/_____|
#
# ---------------------------------------------------------------------------------
*/
/*
# This script is validated on:
# MAX96717F
# MAX96724F
# Please refer to the Errata sheet for each device.
# ---------------------------------------------------------------------------------
*/
// GMSL-A / Serializer: MAX96717F (Tunnel Mode) / Mode: 1x4 / Device Address: 0x84 / Multiple-VC Case: Single VC / Multiple-VC Pipe Sharing: N/A
// PipeZ:
// Input Stream: VC0 RAW12 PortB (D-PHY)
// Deserializer: MAX96724F / Mode: 1x4A + 2x2 / Device Address: 0x5C
// Pipe0:
// GMSL-A Input Stream: VC0 RAW12 PortB - Output Stream: VC0 RAW12 PortA (D-PHY)
0x04,0x5C,0x04,0x0B,0x00, // BACKTOP : BACKTOP12 | CSI_OUT_EN (CSI_OUT_EN): CSI output disabled
// Video Transmit Configuration for Serializer(s)
0x04,0x84,0x00,0x02,0x03, // DEV : REG2 | VID_TX_EN_Z (VID_TX_EN_Z): Disabled
//
// INSTRUCTIONS FOR SERIALIZERS MAX96717F IN BROADCAST MODE
//
// I2C Address Translation
0x04,0x84,0x00,0x42,0x98, // CC : I2C_2 | SRC_A (SRC_A): 0x4C
0x04,0x84,0x00,0x43,0x20, // CC : I2C_3 | DST_A (DST_A): 0x90
0x04,0x84,0x00,0x44,0x44, // CC : I2C_4 | SRC_B (SRC_B): 0x22
0x04,0x84,0x00,0x45,0x40, // CC : I2C_5 | DST_B (DST_B): 0x20
// MIPI DPHY Configuration
0x04,0x84,0x03,0x30,0x00, // MIPI_RX : MIPI_RX0 | (Default) RSVD (Port Configuration): 1x4
0x04,0x84,0x03,0x83,0x80, // MIPI_RX_EXT : EXT11 | (Default) Tun_Mode (Tunnel Mode): Enabled
0x04,0x84,0x03,0x31,0x30, // MIPI_RX : MIPI_RX1 | (Default) ctrl1_num_lanes (Port B - Lane Count): 4
0x04,0x84,0x03,0x32,0xE0, // MIPI_RX : MIPI_RX2 | (Default) phy1_lane_map (Lane Map - PHY1 D0): Lane 2 | (Default) phy1_lane_map (Lane Map - PHY1 D1): Lane 3
0x04,0x84,0x03,0x33,0x04, // MIPI_RX : MIPI_RX3 | (Default) phy2_lane_map (Lane Map - PHY2 D0): Lane 0 | (Default) phy2_lane_map (Lane Map - PHY2 D1): Lane 1
0x04,0x84,0x03,0x34,0x00, // MIPI_RX : MIPI_RX4 | (Default) phy1_pol_map (Polarity - PHY1 Lane 0): Normal | (Default) phy1_pol_map (Polarity - PHY1 Lane 1): Normal
0x04,0x84,0x03,0x35,0x00, // MIPI_RX : MIPI_RX5 | (Default) phy2_pol_map (Polarity - PHY2 Lane 0): Normal | (Default) phy2_pol_map (Polarity - PHY2 Lane 1): Normal | (Default) phy2_pol_map (Polarity - PHY2 Clock Lane): Normal
// Controller to Pipe Mapping Configuration
0x04,0x84,0x03,0x08,0x64, // FRONTTOP : FRONTTOP_0 | (Default) RSVD (CLK_SELZ): Port B | (Default) START_PORTB (START_PORTB): Enabled
0x04,0x84,0x03,0x11,0x40, // FRONTTOP : FRONTTOP_9 | (Default) START_PORTBZ (START_PORTBZ): Start Video
0x04,0x84,0x03,0x15,0x00, // (Default) (independent_vs_mode): Disabled
// Pipe Configuration
0x04,0x84,0x00,0x5B,0x00, // CFGV__VIDEO_Z : TX3 | TX_STR_SEL (TX_STR_SEL Pipe Z): 0x0
//
// INSTRUCTIONS FOR DESERIALIZER MAX96724F
//
// Video Pipes And Routing Configuration
0x04,0x5C,0x00,0xF0,0x60, // VIDEO_PIPE_SEL : VIDEO_PIPE_SEL_0 | (Default) VIDEO_PIPE_SEL_0 (Pipe 0 GMSL2 PHY): A | VIDEO_PIPE_SEL_0 (Pipe 0 Input Pipe): X
0x04,0x5C,0x00,0xF4,0x01, // VIDEO_PIPE_SEL : VIDEO_PIPE_EN | (Default) VIDEO_PIPE_EN (Video Pipe 0): Enabled | VIDEO_PIPE_EN (Video Pipe 1): Disabled | VIDEO_PIPE_EN (Video Pipe 2): Disabled | VIDEO_PIPE_EN (Video Pipe 3): Disabled | STREAM_SEL_ALL (Stream Select All): Disabled
// Double Mode Configuration
// MIPI DPHY Configuration
0x04,0x5C,0x08,0xA0,0x08, // MIPI_PHY : MIPI_PHY0 | phy_4x2 (Port Configuration): 1x4A + 2x2
0x04,0x5C,0x09,0x4A,0x50, // MIPI_TX__1 : MIPI_TX10 | CSI2_LANE_CNT (Port A - Lane Count): 2
0x04,0x5C,0x08,0xA3,0xE4, // MIPI_PHY : MIPI_PHY3 | (Default) phy0_lane_map (Lane Map - PHY0 D0): Lane 0 | (Default) phy0_lane_map (Lane Map - PHY0 D1): Lane 1 | (Default) phy1_lane_map (Lane Map - PHY1 D0): Lane 2 | (Default) phy1_lane_map (Lane Map - PHY1 D1): Lane 3
0x04,0x5C,0x08,0xA5,0x00, // MIPI_PHY : MIPI_PHY5 | (Default) phy0_pol_map (Polarity - PHY0 Lane 0): Normal | (Default) phy0_pol_map (Polarity - PHY0 Lane 1): Normal | (Default) phy1_pol_map (Polarity - PHY1 Lane 0): Normal | (Default) phy1_pol_map (Polarity - PHY1 Lane 1): Normal | (Default) phy1_pol_map (Polarity - PHY1 Clock Lane): Normal
0x04,0x5C,0x09,0x43,0x07, // MIPI_TX__1 : MIPI_TX3 | DESKEW_INIT (Controller 1 Auto Initial Deskew): Disabled
0x04,0x5C,0x09,0x44,0x01, // MIPI_TX__1 : MIPI_TX4 | DESKEW_PER (Controller 1 Periodic Deskew): Disabled
0x04,0x5C,0x1D,0x00,0xF4, // (config_soft_rst_n - PHY1): 0x0
// This is to set predefined (coarse) CSI output frequency
// CSI Phy 1 is 1500 Mbps/lane.
0x04,0x5C,0x1D,0x00,0xF4, // (Default)
0x04,0x5C,0x04,0x18,0x2F, // (Default)
0x04,0x5C,0x1D,0x00,0xF5, // | (Default) (config_soft_rst_n - PHY1): 0x1
0x04,0x5C,0x08,0xA2,0x34, // MIPI_PHY : MIPI_PHY2 | phy_Stdby_n (phy_Stdby_2): Put PHY2 in standby mode | phy_Stdby_n (phy_Stdby_3): Put PHY3 in standby mode
// Tunnel Mode Configuration
0x04,0x5C,0x08,0xCA,0xE5, // MIPI_PHY : MIPI_CTRL_SEL | MIPI_CTRL_SEL_0 (MIPI Controller Pipe 0): 0x1
0x04,0x5C,0x09,0x39,0x10, // MIPI_TX__0 : MIPI_TX57 | (Default) TUN_DEST (Tunneling Destination Pipe 0): 0x1
0x04,0x5C,0x09,0x36,0x09, // MIPI_TX__0 : MIPI_TX54 | TUN_EN (Pipe 0 Tunnel Mode): Enabled
0x04,0x5C,0x09,0x39,0x50, // MIPI_TX__0 : MIPI_TX57 | DIS_AUTO_TUN_DET (Pipe 0 Disable Auto Tunnel Detection): Enabled
// Link Initialization for Deserializer
0x04,0x5C,0x00,0x06,0xF1, // DEV : REG6 | (Default) LINK_EN_A (LINK_EN_A): Enabled | LINK_EN_B (LINK_EN_B): Disabled | LINK_EN_C (LINK_EN_C): Disabled | LINK_EN_D (LINK_EN_D): Disabled
0x04,0x5C,0x00,0x03,0xFE, // DEV : REG3 | (Default) DIS_REM_CC_A (GMSL Link A I2C Port 0): Enabled | DIS_REM_CC_B (GMSL Link B I2C Port 0): Disabled | DIS_REM_CC_C (GMSL Link C I2C Port 0): Disabled | DIS_REM_CC_D (GMSL Link D I2C Port 0): Disabled
0x00,0x01, // Warning: The actual recommended delay is 5 usec.
0x04,0x5C,0x04,0x0B,0x02, // BACKTOP : BACKTOP12 | CSI_OUT_EN (CSI_OUT_EN): CSI output enabled
// Video Transmit Configuration for Serializer(s)
0x04,0x84,0x00,0x02,0x43, // DEV : REG2 | VID_TX_EN_Z (VID_TX_EN_Z): Enabled
// Deserializer: MAX96724F / Mode: 1x4A + 2x2 / Device Address: 0x5C
// Pipe0:
// GMSL-A Input Stream: VC0 RAW12 PortB - Output Stream: VC0 RAW12 PortA (D-PHY)
0x04,0x5C,0x04,0x0B,0x00, // BACKTOP : BACKTOP12 | CSI_OUT_EN (CSI_OUT_EN): CSI output disabled
// Video Transmit Configuration for Serializer(s)
0x04,0x84,0x00,0x02,0x03, // DEV : REG2 | VID_TX_EN_Z (VID_TX_EN_Z): Disabled
//
// INSTRUCTIONS FOR SERIALIZERS MAX96717F IN BROADCAST MODE
//
// I2C Address Translation
0x04,0x84,0x00,0x42,0x98, // CC : I2C_2 | SRC_A (SRC_A): 0x4C
0x04,0x84,0x00,0x43,0x20, // CC : I2C_3 | DST_A (DST_A): 0x90
0x04,0x84,0x00,0x44,0x44, // CC : I2C_4 | SRC_B (SRC_B): 0x22
0x04,0x84,0x00,0x45,0x40, // CC : I2C_5 | DST_B (DST_B): 0x20
// MIPI DPHY Configuration
0x04,0x84,0x03,0x30,0x00, // MIPI_RX : MIPI_RX0 | (Default) RSVD (Port Configuration): 1x4
0x04,0x84,0x03,0x83,0x80, // MIPI_RX_EXT : EXT11 | (Default) Tun_Mode (Tunnel Mode): Enabled
0x04,0x84,0x03,0x31,0x30, // MIPI_RX : MIPI_RX1 | (Default) ctrl1_num_lanes (Port B - Lane Count): 4
0x04,0x84,0x03,0x32,0xE0, // MIPI_RX : MIPI_RX2 | (Default) phy1_lane_map (Lane Map - PHY1 D0): Lane 2 | (Default) phy1_lane_map (Lane Map - PHY1 D1): Lane 3
0x04,0x84,0x03,0x33,0x04, // MIPI_RX : MIPI_RX3 | (Default) phy2_lane_map (Lane Map - PHY2 D0): Lane 0 | (Default) phy2_lane_map (Lane Map - PHY2 D1): Lane 1
0x04,0x84,0x03,0x34,0x00, // MIPI_RX : MIPI_RX4 | (Default) phy1_pol_map (Polarity - PHY1 Lane 0): Normal | (Default) phy1_pol_map (Polarity - PHY1 Lane 1): Normal
0x04,0x84,0x03,0x35,0x00, // MIPI_RX : MIPI_RX5 | (Default) phy2_pol_map (Polarity - PHY2 Lane 0): Normal | (Default) phy2_pol_map (Polarity - PHY2 Lane 1): Normal | (Default) phy2_pol_map (Polarity - PHY2 Clock Lane): Normal
// Controller to Pipe Mapping Configuration
0x04,0x84,0x03,0x08,0x64, // FRONTTOP : FRONTTOP_0 | (Default) RSVD (CLK_SELZ): Port B | (Default) START_PORTB (START_PORTB): Enabled
0x04,0x84,0x03,0x11,0x40, // FRONTTOP : FRONTTOP_9 | (Default) START_PORTBZ (START_PORTBZ): Start Video
0x04,0x84,0x03,0x15,0x00, // (Default) (independent_vs_mode): Disabled
// Pipe Configuration
0x04,0x84,0x00,0x5B,0x00, // CFGV__VIDEO_Z : TX3 | TX_STR_SEL (TX_STR_SEL Pipe Z): 0x0
//
// INSTRUCTIONS FOR DESERIALIZER MAX96724F
//
// Video Pipes And Routing Configuration
0x04,0x5C,0x00,0xF0,0x60, // VIDEO_PIPE_SEL : VIDEO_PIPE_SEL_0 | (Default) VIDEO_PIPE_SEL_0 (Pipe 0 GMSL2 PHY): A | VIDEO_PIPE_SEL_0 (Pipe 0 Input Pipe): X
0x04,0x5C,0x00,0xF4,0x01, // VIDEO_PIPE_SEL : VIDEO_PIPE_EN | (Default) VIDEO_PIPE_EN (Video Pipe 0): Enabled | VIDEO_PIPE_EN (Video Pipe 1): Disabled | VIDEO_PIPE_EN (Video Pipe 2): Disabled | VIDEO_PIPE_EN (Video Pipe 3): Disabled | STREAM_SEL_ALL (Stream Select All): Disabled
// Double Mode Configuration
// MIPI DPHY Configuration
0x04,0x5C,0x08,0xA0,0x08, // MIPI_PHY : MIPI_PHY0 | phy_4x2 (Port Configuration): 1x4A + 2x2
0x04,0x5C,0x09,0x4A,0x50, // MIPI_TX__1 : MIPI_TX10 | CSI2_LANE_CNT (Port A - Lane Count): 2
0x04,0x5C,0x08,0xA3,0xE4, // MIPI_PHY : MIPI_PHY3 | (Default) phy0_lane_map (Lane Map - PHY0 D0): Lane 0 | (Default) phy0_lane_map (Lane Map - PHY0 D1): Lane 1 | (Default) phy1_lane_map (Lane Map - PHY1 D0): Lane 2 | (Default) phy1_lane_map (Lane Map - PHY1 D1): Lane 3
0x04,0x5C,0x08,0xA5,0x00, // MIPI_PHY : MIPI_PHY5 | (Default) phy0_pol_map (Polarity - PHY0 Lane 0): Normal | (Default) phy0_pol_map (Polarity - PHY0 Lane 1): Normal | (Default) phy1_pol_map (Polarity - PHY1 Lane 0): Normal | (Default) phy1_pol_map (Polarity - PHY1 Lane 1): Normal | (Default) phy1_pol_map (Polarity - PHY1 Clock Lane): Normal
0x04,0x5C,0x09,0x43,0x07, // MIPI_TX__1 : MIPI_TX3 | DESKEW_INIT (Controller 1 Auto Initial Deskew): Disabled
0x04,0x5C,0x09,0x44,0x01, // MIPI_TX__1 : MIPI_TX4 | DESKEW_PER (Controller 1 Periodic Deskew): Disabled
0x04,0x5C,0x1D,0x00,0xF4, // (config_soft_rst_n - PHY1): 0x0
// This is to set predefined (coarse) CSI output frequency
// CSI Phy 1 is 1500 Mbps/lane.
0x04,0x5C,0x1D,0x00,0xF4, // (Default)
0x04,0x5C,0x04,0x18,0x2F, // (Default)
0x04,0x5C,0x1D,0x00,0xF5, // | (Default) (config_soft_rst_n - PHY1): 0x1
0x04,0x5C,0x08,0xA2,0x34, // MIPI_PHY : MIPI_PHY2 | phy_Stdby_n (phy_Stdby_2): Put PHY2 in standby mode | phy_Stdby_n (phy_Stdby_3): Put PHY3 in standby mode
// Tunnel Mode Configuration
0x04,0x5C,0x08,0xCA,0xE5, // MIPI_PHY : MIPI_CTRL_SEL | MIPI_CTRL_SEL_0 (MIPI Controller Pipe 0): 0x1
0x04,0x5C,0x09,0x39,0x10, // MIPI_TX__0 : MIPI_TX57 | (Default) TUN_DEST (Tunneling Destination Pipe 0): 0x1
0x04,0x5C,0x09,0x36,0x09, // MIPI_TX__0 : MIPI_TX54 | TUN_EN (Pipe 0 Tunnel Mode): Enabled
0x04,0x5C,0x09,0x39,0x50, // MIPI_TX__0 : MIPI_TX57 | DIS_AUTO_TUN_DET (Pipe 0 Disable Auto Tunnel Detection): Enabled
// Link Initialization for Deserializer
0x04,0x5C,0x00,0x06,0xF1, // DEV : REG6 | (Default) LINK_EN_A (LINK_EN_A): Enabled | LINK_EN_B (LINK_EN_B): Disabled | LINK_EN_C (LINK_EN_C): Disabled | LINK_EN_D (LINK_EN_D): Disabled
0x04,0x5C,0x00,0x03,0xFE, // DEV : REG3 | (Default) DIS_REM_CC_A (GMSL Link A I2C Port 0): Enabled | DIS_REM_CC_B (GMSL Link B I2C Port 0): Disabled | DIS_REM_CC_C (GMSL Link C I2C Port 0): Disabled | DIS_REM_CC_D (GMSL Link D I2C Port 0): Disabled
0x00,0x01, // Warning: The actual recommended delay is 5 usec.
0x04,0x5C,0x04,0x0B,0x02, // BACKTOP : BACKTOP12 | CSI_OUT_EN (CSI_OUT_EN): CSI output enabled
// Video Transmit Configuration for Serializer(s)
0x04,0x84,0x00,0x02,0x43, // DEV : REG2 | VID_TX_EN_Z (VID_TX_EN_Z): Enabled
