Category: Hardware
Product Number: LTC6820
I have modified the POL pin on the chip I am using by soldering it to 5V and the PHA to GND however using the logic analyser, the clock signal is visually not being pulled high. On the other hand, the signal from the dev board (LPC55S28) using MCUXpresso shows that the clock signal is being pulled high when run and I am receiving data from the end sensor which suggests that it is receiving the correct clock signal. Please can someone assist?
Channels 0-3 are between Master devices, 4-7 between Slave devices
Digital signals:
Analog Signals:
