In my design we are using ADN4624BRNZ IC for camlink interface(x4 data lines, x1 Clk) isolation with operating speed 595 MHz. Both sides ADN4624BRNZ Refresh pins are connected to GND Pin.
Note: All input and output dates lines are length matched.
If we are driving incremental data pattern using ADN4654 IC (driving packetized data from FPGA) and trying to receive the same in My board (ADN4624BRNZ receiver) but whatever data we are receiveing it is not proper.
sometimes receving data is shifed and sometimes Duty cycle of the signal is getting changed than original expected signal. Even if we are sending simple clock on all the lines, then clock is getiing shifted or sometimes On Time is more.
but when we tried pulling Refresh pin to vdd then incremental data was receiving properly, and everything is working as expected. Can any one explain how the refresh pin is acting in both cases.