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ADuM4121 High-Side Circuit Design

Category: Hardware
Product Number: ADuM4121
Software Version: N/A

Hello all...looking for some advice concerning a design with the ADuM4121.  I have attached a schematic of the system.  The input is a HV Capacitor charged to upwards of 1.5 kV, and the idea is to control it's discharge in pulses as short as 500ns.  The rub in the design is that during the ON conduction of the SiC MOSFET, a 45 kV HV Capacitor bank discharges to the same device, with the discharge pulse lasting about 5us (5x10^-6 seconds).  This is the reason for the 10 mH inductor, along with the Schottkey Diode and 1 k-Ohm resistor - limit the current from the 45 kV pulse and clamp it so it doesn't destroy the SiC MOSFET, even if the SiC MOSFET is rated at 1.7 kV.  The rest of the circuit is the control for the SiC MOSFET gate, which is where the ADuM4121 comes in.  On the low-side of the ADuM4121, the circuit is powered by 3.3 Vdc from a RECOM AC/DC brick, and the on/off signal is controlled by a 5 Vdc (high) / 0 Vdc (low) Arbitrary Waveform Generator (AWG).  Because this is a high-side switching event, with the Schottkey Diode creating the low-side connection to the SiC MOSFET, the high-side of the ADuM4121 is setup with a bootstrap supply through D2 and R1, with supply buffering from the caps C2 & C3 tied to ground and C4 & C5 floating with the SiC MOSFET Source.  The bootstrap supply for the high-side is also a RECOM AC/DC brick, but its output is 15 Vdc; after D2, the voltage drops to the mid-14 Vdc range, which is expected.

I need to know if my second ADuM4121 that I've tried is also shot, or if my design needs improvement.  What I'm seeing is that Pin 6 (output) is always in the 12-14 Vdc range without any signal to Pin 2 (low-side CMOS logic input).  Pin 3 (- input differential) is tied to GND so that Pin 2 (+ input differential) acts as a single positive trigger.  For troubleshooting, I've even connected a 10 k-Ohm resistor between Pin 2 (+ input differential) and GND, so that this input isn't floating when I don't have the AWG connected.  However, the voltage at Pin 5 (high-side GND) continues to be 13-14 Vdc, while Pin 8 (high-side VDD) is mid-14 Vdc - the same as the D2 output, as expected.  I have disconnected the ADuM4121 from the SiC MOSFET and the rest of the follow-on circuitry, and there is no effect on getting a waveform out of Pin 6 of the ADuM4121 when the AWG pulses Pin 2 of the ADuM4121 with 0-5 Vdc.

I have also tried, for troubleshooting, to ground the floating side of C4 & C5 via a 100 k-Ohm resistor to GND.

Honestly, I feel as though I'm missing something fundamental and obvious, but I'm in the forest and all I see are trees; I'm praying that an outside perspective might help me to understand what I have going on wrong with this circuit...if maybe I've just got a second bad ADuM4121 installed.

v/r

Tim Klein, PE, CID

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  • Hi Kleingineer,

    It's not clear to me in the schematic you shared how the bootstrap works.
    The Source terminal of Q1 (GND2 of U1) needs to be pulled to DGND level (at least periodically) through a low impedance path to allow for C4 and C5 to charge quickly.
    This usually happens when the low-side switch in an half bridge configuration is ON.

    Can you measure the voltage between pin 5 and pin 8 of U1 probing directly on the device? 

    As a debug test: what happen if you disconnect Q1 and short pin 5 of U1 directly to DGND?


    Best regards,


  • LMartini,
    I apologize for any delay in responding - thank you for being quick with your response.
    To answer the first question: What is the voltage between pin 5 and pin 8 of U1 (ADuM4121) probing directly on the device? The answer is 0.79 Vdc.
     
    The second question: What happens when Q1 is disconnected and Pin 5 of U1 (ADuM4121) is shorted directly to DGND?  First, the voltage between pin 5 and pin 8 of U1 (ADuM4121) probing directly on the device is 14.55 Vdc.  This is expected as the RECOM AC/DC supply to this side of the circuit is 15.17 Vdc, and there's a roughly 0.6 Vdc drop across D2.  When Pin 6 (Output) or Pin 7 (Clamp) are monitored with an o-scope as Pin 2 (+ differential input) is brought high to 5.0 Vdc, these pins follow at ~14.5 Vdc.  This tells me that the ADuM4121 is functional and behaving as it should.
     
    Based on this analysis, the problem is with the bootstrap circuit, in that the C4 & C5 low-side needs to be brought to DGND prior to switching in order to properly charge and then switch the ADuM4121 high-side.  Unless you or others have any additional suggestions, I'll iterate the design to account for this and repost when it is completed.
     
    v/r
    Kleingineer
  • Complete redesign using 2x ADuM4121's so that the bootstrap circuit would work.  I fed the Trigger Input into U2 on it's VI- (- differential input) so that when the trigger goes high, the lower MOSFET turns OFF.  I haven't examined the timing, so hopefully there won't be much, if any, shoot-thru.  Testing of this next iteration of the board should be complete in about 2 or 3 weeks.  I'll try to write back when testing is complete.

    -Kleingineer

  • Testing completed and the unit shipped at the beginning of August, just now getting to writing a response 2-3 weeks later.  The logic employed for U1 and U2 is functional, and because Q2 brings the system low on the switch (high) side, the bootstrap design works as intended.  Thank you for your assistance and pointer - I would have forgotten about needing to bring the bootstrap low for a charging time if it hadn't been for the suggestion.

    -Kleingineer

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  • Testing completed and the unit shipped at the beginning of August, just now getting to writing a response 2-3 weeks later.  The logic employed for U1 and U2 is functional, and because Q2 brings the system low on the switch (high) side, the bootstrap design works as intended.  Thank you for your assistance and pointer - I would have forgotten about needing to bring the bootstrap low for a charging time if it hadn't been for the suggestion.

    -Kleingineer

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