Not getting SPI signal at Side 2 of ADuM3151

Hello Gaurav,

   The supply current the ADuM3151 will draw depends on the supply voltage and data rate.  Datasheet Figures 9 and 12 show typically values of I_DD1 and I_DD2 for 3.3V and 5V supply voltages and different data rates. 

   There could be many reasons for why you're not getting the expected SPI signals on side 2.  I'm assuming that this is a new design which you're testing for the first time (if not, this would completely change the troubleshooting tree).  Some (perhaps obvious) things to confirm/check include:

• Does the actual physical circuit match the schematic?
  • Do the supply and reference for each side correctly line up (e.g. 3.3V node's reference return is PROC_GND, and DIO_3.3's return is 24GND)?
  • No solder bridges/assembly errors are present...
• Are the expected V_DD supplies present on sides 1 & 2? 
• Are the side 2 outputs driven or high-Z?  Same for side 1 outputs.
  • If they are high-Z, this might suggest that the part may not be powered correctly
  • If they are driven, do any of them follow their inputs?

Eric

Hi Eric,

Thanks for your response!!

The supply current the ADuM3151 will draw depends on the supply voltage and data rate.  Datasheet Figures 9 and 12 show typically values of IDD1 and IDD2 for 3.3V and 5V supply voltages and different data rates. 

As per Fig 9 and 12, IDD1: 2.8mA (1.5MHz) and IDD2: 5.4mA (1.5 MHz)

Is our observation correct or not?

Does the actual physical circuit match the schematic?

Yes, we’re only connecting TI uC evaluation board to the adapter board having isolator soldered on it (attached image_01), i.e. giving supply 3.3V, GND and SPI clock signal from the board for now.

Do the supply and reference for each side correctly line up (e.g. 3.3V node's reference return is PROC_GND, and DIO_3.3's return is 24GND)?

Yes, the supply and GND are lining up correctly. The 24GND is so named because it is also used with 24V supply used with another IC on the second side of the isolator (which is not connected currently).

No solder bridges/assembly errors are present...

No assembly errors can be seen

Are the expected VDD supplies present on sides 1 & 2? 

Yes, cross-checked the supplies on both sides with multi-meter as 3.2V

Are the side 2 outputs driven or high-Z?  Same for side 1 outputs

The side 2 outputs are not high-Z but do not follow the inputs.

On Side 2 of the isolator, we’re giving 8mA as supply current (see image_02) and the current consumed is 5.4mA ( image_03) but when we reset the TI eval board, the LED of constant current(CC) starts glowing in the power supply  and voltage drops from 3.3V to 2.6V (image_04) and we’re not getting any outputs on the signals of Side 2.

On the Side 1 of the isolator, the SPI clock signal is shown in image_05.

Thanks,

Gaurav

D

Hi Gaurav,

 It appears from the 1st picture of your hardware that you do not have a VDD2 supply connected; however, your other comments seem to suggest that it is connected, so I'll assume it just wasn't connected when the picture was being taken.  Remember that the ADuM3151 doesn't include an isolated supply and so the part won't work unless both supplies are present.

 Its possible that the current limit on your supply is set too low relative to the needs of the part and I'd suggest raising the current limit.  8mA only a few mA above the expected draw for the part and I'd be suspicious about how accurate the current limit of your supply is - I'm not familiar with that instrument, but based on the display's scale, 8mA looks like it may be approaching its limits of precision...  I'd start with something closer to 15-20mA. 

Eric

Hi Eric,

As per the datasheet, the max supply current that we can give for 1MHz grade is 8mA which is why we kept the current to that value.

However, even for 17MHz range, the max supply current value is 17-18mA.

Thanks,

Gaurav

Hi Gaurav,

  From your pictures, I'm assuming your power supply for the isolated side is a Grundig PN300.  I found a data sheet for it on-line (https://docs.rs-online.com/24ca/0900766b80f3fd06.pdf ) which lists the current setting and measurement accuracy as +/-(0.5% +10mA).  Note that the uncertainty due to the offset is larger than the setting of 8mA.

   You mentioned that when the input is idle, the power supply provides 5.4mA and is not in current limit.  This suggests that there is no fault on the supply such as a solder bridge, or connection error and that the part is likely not damaged.  When you apply the SCL input from the processor evaluation board, the ADuM3151 would be expected to draw more current and you report that the power supply is going into current limit at this time.   The supply's output voltage of 2.62V when in current limit is very close to the ADuM3151's typical UVLO of 2.6V.  I suspect that when the ADuM3151 starts to draw more current, the supply current limits and its output voltage collapses until the ADuM3151's UVLO is activated turning off the part which reduces the current.  With the lower current draw, the supply then leaves current limit and allows the voltage to increase until the ADuM3151's UVLO resets allowing it to become active again thus drawing more current and repeating the cycle...

  I believe increasing the current limit on the supply will resolve this issue.

Eric

Hi Eric,

Thanks for your support!!

When giving a 15mA supply on side 2 of the isolator, it consumes 4mA, and instead of getting the 1.5MHz SCLK on side 2, we're getting 50Hz signal on the corresponding signal pin of the other side of the isolator.

This time, we did this validation on EVAL-ADUM3151Z, still we are getting same issue.

Please advise!!

Thanks,

Gaurav

Hi Gaurav,

  Measuring 50Hz for the output channel seems to suggest that your scope probe is measuring an open circuit / power supply line "noise".

  How exactly are your scope probes connected to the test circuit?  Remember that the isolator has separate "grounds" which can be problematic when measuring with a single oscilloscope, especially if you are using standard probes which have their probe reference/GND leads connected to earth via the scope's chassis/PE.

 Using the standard probes to measure both sides is OK as long as you don't have a voltage across the barrier, but since the scope will only have a single GND (also connected through chassis to earth), the isolator's GND1 needs to be connected to GND2 (either through an intentional jumper - better since you know you added it and would protect the scope or through the scope probe GND leads/connections - potentially problematic since it may escape notice and kill your scope when a barrier voltage is later applied ).  

  If shorting the isolation barrier (and connecting that point to earth) isn't possible, then you'll need to measure one side at a time, assuming that you can individually tie each side to earth through the scope's ground reference lead/connection.

  Alternatively, you can use a standard probe on one side of the barrier which is earth grounded and then use an isolated scope probe or a differential probe with sufficient common mode range to measure the non-earth grounded side of the barrier.   

  Depending on the barrier voltage, you can also create an effective differential probe by using 2 probes to measure the isolated side's signal and its GND/reference and then using the scope math to subtract signal ch - ref ch.  When doing this technique, connect both probes to the non-isolated GND.  Note that the input attenuators for these two probes need to be set to allow the barrier voltage + signal to remain within range/on screen.  For low barrier voltages, this can work OK as a cheap diff probe; however, for higher voltages, the high V/div setting will reduce the signal/noise ratio for the measured signal...  Also, the barrier + signal voltage needs to remain within the probe's voltage range...

Eric

Hi Eric,

We are measuring one side at a time, assuming that we can individually tie each side to earth through the scope's ground reference lead/connection.

Gaurav

Hi Gaurav,

   The 50Hz measurement to me strongly suggests a probe is measuring an open circuit picking up the power line's ambient emissions and is not being properly driven by a signal node.

   If you're moving the scope back and forth, that should work if everything is connected correctly. 

   If I had this board in front of me for debugging; I'd do the following steps (some of which you've likely already done):

* re-verify correct construction by using a DMM to ring out each connection from the labeled connection pins to each pin on the IC package.  

* apply VDD supply to both sides, probe IC pins with DMM to verify present and correct.  Also use DMM to verify supply currents are within range.

* Using jumpers to VDD supply, apply known static inputs to all inputs on both sides and measure the output state to verify IC is OK.  Verify each pin is driven as expected.  If there's a question about being driven vs. high-Z; I'd place a large valued 20k pull up or down to bias the output pin opposite the expected state so that the IC has a load to drive against.

Hopefully at this point, I'd have either found an issue to correct or established that the IC is working because the outputs are doing what is expected based on the static inputs.  

If the IC works correctly with the static inputs but not the dynamic switching, then I'd suspect that maybe the issue is with the decoupling capacitor's placement electrically far from the IC.  I assume the decoupling caps are the yellow and black components near the power connector and in that location there is a non-negligible amount of parasitic inductance in the power loop between the capacitor and the IC.  If this hypothesis is correct, then when the IC starts to operate and logic internally is changing state, it will draw an increased amount of current from the decoupling cap.  This di/dt will cause a voltage drop across the parasitic inductance and could cause the UVLO to trigger and/or cause other issues.  Usually, I'd expect that something like this to be more likely to cause glitches, but... 

When I use the breakout /carrier boards like what you've used, I solder at least the smaller valued decoupling cap directly on the board, as close as possible to the IC's power pins.  I'll then place the larger decoupling cap either on the carrier as well or perhaps down on the motherboard close to the IC carrier daughterboard.

Note that ceramic caps typically have a low ESR and so will form a high-Q resonant circuit with the parasitic inductance of the power supply circuit and this resonant circuit has the potential of applying 2x the applied voltage if the power supply is "hot plugged"/connected when energized.  If 2xVdd > Vabsmax, this can quickly kill an IC.  Normally with your 3.3Vdd and Vabsmax=7V, you should be fine in this respect, but...   To prevent this, I will typically add a higher ESR electrolytic cap at the power input where you have the ceramic caps.   This provides both a bit of additional local energy storage as well as damping the resonant ring.  Sometimes when I've skipped this, I've been lucky, but other times, not so lucky...

Eric

                         SPI signal at side 2 of Isolator 

Hi Eric,

Thanks for your valuable support!!

Our problem has been resolved for SPI signal.

Thanks,

Gaurav 

You're welcome and I'm glad to hear its working for you! 

You're welcome and I'm glad to hear its working for you!