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ADN4655 LVDS Voltage Levels

Category: Software
Product Number: ADN4655
Software Version: NA

I am using the ADN4655 to isolate SerDes interface between two FPGAs. One FPGA#1 has Vcm =1.2V and Vd = 350mV while the other FPGA#2 has Vcm = 0.6V and Vd = 550mV.

I am understanding that the ADN4655, since isolated, translation between the two LVDS interface should be feasible.

For the input, as long as the (Vid) swing is more than +/-100mV threshold regardless of the common mode voltage, the receiver will work and understand low and high logic. Correct?

For the output, the Vod is +/-(250mV-450mV), correct? Now assuming there is no AC coupling, what will the common mode voltage be for the output signals? Is it going to be based on the common mode of the FPGA so in FPGA#1 1.2V and FPGA#2 0.6V or is it a constant voltage of 1.17V and AC coupling should be used to level to FPGA#2 voltage?

[edited by: SS636 at 11:05 AM (GMT -4) on 15 Jun 2022]