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ADN4655 LVDS Voltage Levels

Category: Software
Product Number: ADN4655
Software Version: NA

I am using the ADN4655 to isolate SerDes interface between two FPGAs. One FPGA#1 has Vcm =1.2V and Vd = 350mV while the other FPGA#2 has Vcm = 0.6V and Vd = 550mV.

I am understanding that the ADN4655, since isolated, translation between the two LVDS interface should be feasible.

For the input, as long as the (Vid) swing is more than +/-100mV threshold regardless of the common mode voltage, the receiver will work and understand low and high logic. Correct?

For the output, the Vod is +/-(250mV-450mV), correct? Now assuming there is no AC coupling, what will the common mode voltage be for the output signals? Is it going to be based on the common mode of the FPGA so in FPGA#1 1.2V and FPGA#2 0.6V or is it a constant voltage of 1.17V and AC coupling should be used to level to FPGA#2 voltage?

[edited by: SS636 at 11:05 AM (GMT -4) on 15 Jun 2022]
  • Hi,

    Your assumption about the input is correct, as long as the common mode on the input is between 0.5*|VID| and 2.4 - 0.5*|VID| with |VID| >= 100 mV then the input signal will be reliably transferred to the ADN4655 output.

    For the output, the common mode should be per ADN4655, 1.17V, unless the FPGA terminates the high-speed differential input with an applied common mode. If the 0.6V common mode on FPGA 2 is just for its output signal, this isn't something you need to be concerned about for the ADN4655 output as long as FPGA2 can accept 1.17V common mode input.

    If there is an applied common mode of 0.6V at the FPGA2 differential input termination, then using AC coupling is probably the best approach. If you AC couple the ADN4655 inputs you would need to bias the termination to apply a common mode voltage again, but if you are AC coupling the outputs specifically because FPGA2 applies a common mode at its built-in termination, then just the coupling caps on the ADN4655 output should work.

    Best regards,