The bottom scope capture is a magnified version of the top. In each picture, the top trace (A2) is pin 3 of the ADUM1251 (SCL input, side 1) and the bottom trace (A1) is SCL output (side 2). ADUM1251 can only drive SCL on side 2. The problem is this chip inserted a positive clock pulse on side 2 even though the input side is low when this occurred.
My I2C slave is not able to drive SCL and even if it could, I wouldn’t expect such a clean signal. Since this is open drain, it’s highly unlikely something other than the ADUM1251 could drive SCL output on pin 6 high. These are very valid logic voltage levels.
My I2C master is connected to side 1 and my I2C slave is on side 2. For the purpose of this test, I connected grounds for both sides together so I could probe with my scope (scope channel grounds aren’t isolated). SCK =100KHz, 3K pullups on both SDA and SCL for both sides, and everything is 3.3V