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ADUM1251 Extra Clock Pulse

Category: Hardware
Product Number: ADUM1251

The bottom scope capture is a magnified version of the top. In each picture, the top trace (A2) is pin 3 of the ADUM1251 (SCL input, side 1) and the bottom trace (A1) is SCL output (side 2). ADUM1251 can only drive SCL on side 2. The problem is this chip inserted a positive clock pulse on side 2 even though the input side is low when this occurred.

My I2C slave is not able to drive SCL and even if it could, I wouldn’t expect such a clean signal. Since this is open drain, it’s highly unlikely something other than the ADUM1251 could drive SCL output on pin 6 high. These are very valid logic voltage levels.

My I2C master is connected to side 1 and my I2C slave is on side 2. For the purpose of this test, I connected grounds for both sides together so I could probe with my scope (scope channel grounds aren’t isolated). SCK =100KHz, 3K pullups on both SDA and SCL for both sides, and everything is 3.3V

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  • Hi,

    The ADuM1251 is also open drain output. The high states are created by the pull-up resistors typically.

    I would expect SCL2 to be sinking current when SCL1 has a low state present. Is this a one time event?

    Regards,

    Jason

  • It always does this - very repeatable. My theory is it's being caused by some state machine inside the ADUM1251. Could this chip misinterpret this as some type of error which it then performs recovery action which creates this pulse? This is VERY weird.


    When I bypass the ADUM1251, this signal is obviously correct and my master/slave communicate correctly.

  • Hi,

    There are no state machines in the ADuM1251 and the device is protocol agnostic. The SCL channel on the ADuM1250 is just a directional channel. It will simply reproduce the data from the input (SCL1) to the output (SCL2).

    There is a video that explains they operate How I2C Isolators Work

    The input low level looks sufficiently low from the scope capture. You might try measuring closer to the SCL1 pin to see if the voltage is somehow higher closer to the pin. Any chance the isolator vdd supplies are under voltage? When undervoltage, the SCL2 and SDA2 will go high impedance, allowing the pull-ups to raise the bus level.

    Is there anything with a push-pull outputs on Side 2 of the isolator?

    Jason

  • I made a mistake in my diagram - the sides were swapped. The correct image is below. What's happening is the slave is doing "clock stretching". Clock stretching allows the slave to pause the master. The reason it fails on my setup is because SCL on ADUM1251 is unidirectional so the master never sees the "stretch". This also explains why it worked without this isolator.


    This slave is actually a microcontroller so I either need to reconfigure the HAL driver to not use clock stretching or use ADUM1250, which supports driving SCL from both sides.

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  • I made a mistake in my diagram - the sides were swapped. The correct image is below. What's happening is the slave is doing "clock stretching". Clock stretching allows the slave to pause the master. The reason it fails on my setup is because SCL on ADUM1251 is unidirectional so the master never sees the "stretch". This also explains why it worked without this isolator.


    This slave is actually a microcontroller so I either need to reconfigure the HAL driver to not use clock stretching or use ADUM1250, which supports driving SCL from both sides.

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