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ADUM6402CRWZ regulation and noise issues

We had to make some component substitutions and PCB layout changes due to the supply chain issues, and due to lack of availability, substituted the ADUM5402ARWZ we have been using successfully for years with ADUM6402CRWZ.  We did have to make small adjustment to the Viso pin PCB layout connections, but are still using the same capacitors in the same locations as with the ADUM5402ARWZ  (2 x 0.1uF X7R 0603 MLCC caps, 1x 0.01uF X7R 0603 MLCC directly near Pin#16, and 1 x 10uF  X7R 1206MLCC cap directly under (opposite PCB side) of the other capacitors with multiple vias connecting to the power plan and the Viso pin trace.  I realize this may have been considered 'marginal' but it worked very reliably with the ADUM5402ARWZ for years. 

Now, with ADUM6402CRWZ in place, we added a jumper wire (short) from Pin#7  to Vdd 10uF capacitor - it is less than 15mm long.

From a sample size of (12) complete printed circuit assemblies we observe approximately 40% working acceptably.  The remainder seem to exhibit either a Viso regulation problem (regulation begins at 5.0V, becomes unstable and ends up regulating at 4.7V)  - OR- Viso appears to regulate OK at 5.0V (Vdd input at Pin#1 is also 5.0V) but we observe strange oscillations/glitches on one or more of the data pins, even when no data signal  is being applied.  It can appears are triangular, RC type-decay type waveforms on the Viso pins, and correspondingly as data glitches on the Vdd data pins, often with the signal level going from 5.0V to 2.5V or from 0V up to 2.5V.

From looking at other threads on the forum, maybe it is somewhat of a PCB layout issue for regulation - but the ADUM5402 didn't seem to have an issue.  And, it appears at least some of the ADUM6402 seem to be OK with it.  But the cases of the oscillation/noise glitches appearing even when the Viso output appears to be glitch free and stable is very confusing.

I can attach more images if needed.  Here are a few to illustrate what we see on the problematic units.

Component info: ADUM6402CRWZ   #2049*  5129927.1      Vdd = 5.0V, Viso = 5.0V

Viso regulation glitches/level shifts

Viso ends up regulating at 4.7V

2nd -issue mode, Viso seems to regulate OK, but noise/oscillations appear on data channels on device:

Viso regulating at 5.0V

Pin #11 oscillatory noise with no data being driven into it:

resulting glitches appearing on data channels pins # 6,5,4 -  note that it drops from 5.0V to approx 2.5V

On the oscillatory units I have also tried increasing Viso capacitance to 20uF, but still the problem persists.  On some PCAs we have tried replacing the ADUM6402 with another, but as we seem to have less than 50% success rate to begin with, that hasn't usually solved things either.

Any additional help you can provide is much appreciated - Thank you!


  • Please add a 100nF decoupling capacitor between pins 7 and 8 as close to the part as possible. The 15mm of wire length can produce voltage dips as the internal circuits turn-on, change state, etc.  If this voltage is not stable then it is possible for the internal logic to end up in unintended states producing undesirable behavior.

  • I will try this and report back on the outcome. 

    In meantime, I would appreciate your input on my proposed PCB layout changes to improve our chances of success going forward, and permit use of either ADUM5402ARWZ or ADUM6402CRWZ devices for U2 in this PCA.  

    VISO (Pin#16, U2): Previously, C9 and C7 were 0.1uF X7R 100V C0603 caps, C8 was 0.01uF X7R cap.  And a 10uF C1206 X7R cap was on bottom layer of PCA, tied to VISO pad copper area pour with 3 vias.  There is also an internal plane connected to the ViSO net.  I have changed C9 to now be 10uF 10% C1206 as shown so now we should have lots of capacitance directly tied to VISO pin, and also still have the other 10uF tied through (3) vias on the bottomside of the PCA (and internal plane).

    (Pin#7,U2) Previously this had a resistor to be connected to  3.3 or 5.0V.  Now, we have added R18 option (0-ohm r0603) jumper to +5Vdd plane and also added optional  0.1uF C26 10% c0603 bypass capacitor from Pin#7 to the GND reference pour that is connected to Pin#8 as well as internal GND plane).

    The thinking here is we can use ADUM6402 with R18 & C26 installed, or use ADUM5402 and leave R18, C26 open and can either float Pin#7 or tie to desired voltage by other resistor on bottom side of PCA.

  • The circuit layout and provisions to accommodate both parts is good. In general it is best to have the 100nF capacitors on VDD, VL and VISO placed as close to the pins as possible with the shortest loop distance. With this in mind minor improvements could be made by rotating clockwise C7, shifting C26 up and to the left, and rotating 90 deg. either C13 or C11 on the VDD pin. The 10nF and extra 10uF on VISO should not be necessary. the 10uF caps on VDD and VISO should follow the same rules as above if possible.

  • Thank you - this information is very helpful!

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