What is the permitted current into any pin of digital isolator ADuM242E1BRIZ that will not damage the isolation characteristics?

Question

I have an application where I need to protect the isolation of a digital isolator in the event a fault in either of the two circuits that it couples. 
 To achieve this goal 
 
 The left hand side circuit will limit the voltage supply of the left hand side in the event a fault in the left hand side circuit. 
 The right hand side circuit will limit the voltage supply of the right hand side in the event a fault in the right hand side circuit. 
 Each input and output has a protective impedance that will limit the current into or out of a pin in the event a fault and also during normal operation. 
 
 Note that in the event of a fault it is acceptable for the digital isolator to stop working but the isolation characteristics must be preserved however. 
 The data sheet for the ADuM242E1BRIZ in the section "DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS" states that 2.78W can be dissipated without damaging the insulation. However it does not state how much current can flow into or out of pin without damaging the insulation. 
 On the other hand, if I look at the data sheet for MAX22444&ndash;MAX22446, in the section Safety Limits, it states that "Safety Current on any pin = 300mA". This is the information I need! 
 It would also be helpful if you described the structure of the input and output pins (I assume conventional CMOS) and a gave a figure for the current that the clamp diodes (I assume that there are clamp diodes) can conduct under normal operation.

jnaso · Accepted Answer

Hi Rob, 
 Apologies for the delay... Short answer is there are current limits provided in the VDE 0884-11 certifications on the Safety and Regulatory Certification page. Let me explain why considering power limitations in case of a fault is more useful for preserving the integrity of the isolation though. 
 The isolator can be thought of as two parallel systems. The ADuM242E has a multi-layer polyimide barrier that is part of the iCoupler signal isolation technology. Then there is also the mold compound which essentially pots the small internal clearances. Both of those systems need to be intact to keep the expected high voltage performance. 
 A good way to damage the integrity of an isolator is with severe thermal overstress. And a good way to cause excessive heating of an IC is with a latch-up event. Latch-ups can be caused when the datasheet's absolute maximum values are exceeded, and a parasitic SCR is triggered. The interesting thing is its actually the mold compound that will be damaged at a lower temp then the iCoupler barrier technology. Mold compound decomposes above 300C, but note the component certifications from 0884-11 limit the internal temp to only 150C. 
 The mitigation techniques that you've listed above are spot on. Clamping the voltage can keep a latch-up from occurring. Limiting the source impedance prevents excessive power from being dissipated inside the package if some fault in the application occurs. 
 Thinking about the limitations in terms of power is important because it is the heat dissipated inside that package that needs to be limited. Its difficult to say what the characteristics of an IC will be after it is damaged by EOS or a parasitic SCR triggered. It may be easier to consider the fault source voltage an impedance to figure the maximum power that could be dissipated is the isolator package. 
 Regards, 
 Jason)

Electronic Design Services - PartnerZone

Products Mentioned

What is the permitted current into any pin of digital isolator ADuM242E1BRIZ that will not damage the isolation characteristics?