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Part to Part Propagation Delay Skew of ADuM4138

Hi 

We would like to "hard paralleling" two SiC Modules, so the part-to-part delay skew is very important. Unfortunately, we didn't find the maximum time in the datasheet. Please specify the   Propagation Delay Skew.

Kind Regards

Rolf Lerch

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  • Hello,

    I'm am working on getting some numbers for you. We do collect data for skew, since it is a results of propagation delay measurements. From the min/max propagation delay numbers, the part to part skew will be less than the max prop delay minus the min prop delay, which results in a number less than 59 ns. this of course is probably not small enough for your needs. Hopefully I can give you a better skew number once we look at the data.

    For the ADuM4138, hard paralleling of modules is also possible with a single driver, if you are running both SiC modules with the same logic all the time. If you are looking to have one SiC device off for portions of time, it would require two drivers as you suggest. 

    Are the modules you are running very large? The ADuM4138 has a lot of gate drive strength, and might be able to run both modules in parallel with a single gatedriver.

    RSchnell

  • Hello,

     

    Thank you for the super-fast reply! Really appreciate that. And your right – 59ns won’t fit our needs.

    Why don’t you mention it in your Rev. A Datasheet? We first used the values (max. 20ns)  from Rev. PrA. And 20ns would be OK but hardly depends on the parasitics of the layout.The main reason for having “one Driver per Module” is mainly driven by the physical geometry of the inverter. Nevertheless we also like the fact of having a desat/clamp function per single MOS.

    The module are quite large (500A-600A Devices)

     

    Best Regards

     

    Rolf

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  • Hello,

     

    Thank you for the super-fast reply! Really appreciate that. And your right – 59ns won’t fit our needs.

    Why don’t you mention it in your Rev. A Datasheet? We first used the values (max. 20ns)  from Rev. PrA. And 20ns would be OK but hardly depends on the parasitics of the layout.The main reason for having “one Driver per Module” is mainly driven by the physical geometry of the inverter. Nevertheless we also like the fact of having a desat/clamp function per single MOS.

    The module are quite large (500A-600A Devices)

     

    Best Regards

     

    Rolf

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