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ADN465x for 100 Hz to 2kHz LVDS

Hello,

I would like to use one device of the ADN465x family with a LVDS signal with a frequency range 0.1 to 2 kHz. Which device of the ADN465x family has the lowest jitter within the bandwidth  of my application?

Regards

Parents
  • Hello,

    Both ADN4650 and ADN4654 will have similar low jitter in the bandwidth of interest. We've characterized both parts as 387 fs typical for bandwidth 100 Hz to 100 kHz (so less again across 100 Hz to 2 kHz); that's with 10 MHz carrier so if the signal you are sending through is 100 Hz to 2 kHz the setup isn't quite the same, but in any case very low jitter is expected and similar for all parts in ADN465x family.

    Although it's a quad-channel part and designed for up to 2.5 Gbps (1.25 GHz) input signal, I can recommend ADN4624 as well, as it has lower jitter again of typically 225 fs or 270 fs for the same conditions as ADN465x. The lower 225 fs jitter is acheived by disabling the internal refresh signalling.

    Regards,

    Conal

Reply
  • Hello,

    Both ADN4650 and ADN4654 will have similar low jitter in the bandwidth of interest. We've characterized both parts as 387 fs typical for bandwidth 100 Hz to 100 kHz (so less again across 100 Hz to 2 kHz); that's with 10 MHz carrier so if the signal you are sending through is 100 Hz to 2 kHz the setup isn't quite the same, but in any case very low jitter is expected and similar for all parts in ADN465x family.

    Although it's a quad-channel part and designed for up to 2.5 Gbps (1.25 GHz) input signal, I can recommend ADN4624 as well, as it has lower jitter again of typically 225 fs or 270 fs for the same conditions as ADN465x. The lower 225 fs jitter is acheived by disabling the internal refresh signalling.

    Regards,

    Conal

Children
  • Hi Conal,

    Thanks for your reply.

    I think I will take the ADN4652...the jitter level you mentioned is fine for my application ( number of channels, package...fine as well).

    Yes I am sending LVDS with a frequency span of 0.1-2kHz. So very low speed but I read in the datasheet that: " the ADN4651/ADN4652 operate not only at 600 Mbps but also at any arbitrary data rate down to dc." So I am quite confindent about this. 

    However, I have some additional questions:

    - Are there recommended values for the biasing resistor? ( required if the LVDS incoming waveform has Trise>5 ns) Can I use a simple resistor divider network with 10k-10k on Din+ and 10k-8.2k on Din- to assure Vid>100mV?

    - what to do if I have an unused input? put a 100 ohm resistor across Din+ and Din- and nothing on the output?

    - In the recommended PCB layout I just see capacitor. Can a common mode choke improve the performance?

    Thanks a lot 

  • Hi,

    For biasing, I would add just a pull-up on Din+ and pull-down on Din-. Pull-up to 2.5V on Din+ means you could use similar value for pull-up and for pull-down. To ensure minimum of +100 mV you might want 1.2 k pull-up if that's feasible for your interconnect. If you are using both rising/falling edge of clock, be aware that this will add duty cycle distortion due to the positive differential offset.

    For an unused input, it's probably best to tie Din+ to 2.5V and Din- to GND. No termination is necessary, but tying the pins high and low will ensure the output is fixed (positive differential, not chattering). Leaving the output not connected is fine.

    A common mode choke will likely negatively impact the signal integrity, but sometimes it's a useful approach for filtering if there's an off-board connection (stop noise from off-board coupling in, or stop noise from on-board coupling out to another system or causing system EMC issues).

    Regards,

    Conal

  • Thanks again Conan.

    I am afraid I do not understand your reply about the biasing resistors. Can you share a drawing of the circuit?

    Regarding the others: got them!