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# Adum3223 why is the output VOA VOB high when vdd1 = 5V and via VIB = 3.3V? In the specification, when vdd1 = 5V, via VIB needs to be greater than 0.7 * vdd1 = 0.7 * 5V = 3.5V, and the output above 3.5V is high level?

Adum3223 why is the output VOA VOB high when vdd1 = 5V and via VIB = 3.3V? In the specification, when vdd1 = 5V, via VIB needs to be greater than 0.7 * vdd1 = 0.7 * 5V = 3.5V, and the output above 3.5V is high level?

When vdd1 = 5V, is via VIB applicable when the maximum voltage is only 3.3V?

• Hello,

The input thresholds should be interpreted as meaning that if a voltage on the input pin is above 0.7*VDD1, the output will for sure go high. If a voltage is below 0.3*VDD1, the output will for sure go low. The exact threshold where edges occur happens between the 0.3*VDD1 and 0.7*VDD1 voltage. The datasheet is guaranteeing that a voltage above 0.7*VDD1 will set the output high.

A high output with an input of 3.3 V is allowable, and expected. What would not be expected is if the output were to be high with an input voltage below 0.3*VDD1=1.5V.

RSchnell

• When VDD=5V, 3.3V is less than 0.7*VDD=3.5V, 0.4*VDD~0.6*VDD is the output high level or low level?

When VDD=5V, VIA=3.3V 3.3V less than 3.5V less than 0.7*VDD=3.5V, why is it high at this time? Isn't it necessary to reach the voltage above 0.7*VDD to output the high level?