ADN4624 Isolator voltage rating

Hi Team
we are working on CX3 and Deserializer. 


I have a doubt about the working voltage of the ADN4624 Isolator. https://www.analog.com/media/en/technical-documentation/data-sheets/adn4624.pdf


In the Datasheet it is mentioned ABSOLUTE MAXIMUM RATINGS for VDD1 to GND1/VDD2 to GND2 are -0.3V to 2V  (On page 8). 


Also in the recommended voltage of ADN4624 is about 1.7V to 1.9V. If I use 1.8V, this will damage the CX3 MIPI port. 

For our application, we need to operate the Isolator to 1.2V.

Is it possible that ADN4624 works at 1.2V.?

If not, will you please recommend the isolator for our application? 


1. MIPI isolator (2Gbps transfer rate per lane)
2. 5kv isolation is needed.
3. Operating working voltage required is 1.2V.



Content
[edited by: Praveen99 at 10:34 AM (GMT -4) on 23 Jul 2021]
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  • +1
    •  Analog Employees 
    on Jul 26, 2021 1:10 PM

    Hi Praveen,

    The ADN4624 requires a 1.8V power supply on each side to power the I/O and digital isolator core. The I/O voltage on the other hand supports low voltage differential signals, specifically LVDS but others such as CML (current mode logic) can be connected with a coupling network.

    Our circuit note CN-0422 has an example coupling network for CML<>LVDS using ADN4654 (HDMI uses CML for the physical layer TMDS data/clock); ADN4624 will be similar. So it might be useful to try and isolate the V-by-One inputs of THCV242 instead of the MIPI-CSI2 outputs, although ADN4624 will limit the bit rate to 2.5 Gbps maximum (the four channels should allow both V-by-One inputs though).

    The reason that it's challenging to isolate the MIPI-CSI2 directly is that as you mention, there are 1.2V signals used. In fact these are single-ended LVCMOS (1.2V) control signals, multiplexed on the same I/O lines as high-speed differential data (two single ended signals per differential pair). ADN4624 can only directly isolate the high-speed differential data, so to fully realize isolated MIPI-CSI2, a detection circuit to differentiate between HS positive/negative differential and the low power single ended signal states (00,01,10,11) would be needed, to control a MUX on the output side of ADN4624, as well as switching in a parallel isolation path for the 1.2V control signals using standard digital isolators (these only work down to 1.8V so level shifters would be required too). The timing requirements to handle the propagation delays for the ADN4624, level-shifters+standard isolator, and isolated control signal and MUX would all have to be considered.

    Overall trying to isolate V-by-One directly is probably a better option if the interface is short (ADN4624 has no RX eq) and can be capped at 2.5 Gbps.

    Best regards,

    Conal

Reply
  • +1
    •  Analog Employees 
    on Jul 26, 2021 1:10 PM

    Hi Praveen,

    The ADN4624 requires a 1.8V power supply on each side to power the I/O and digital isolator core. The I/O voltage on the other hand supports low voltage differential signals, specifically LVDS but others such as CML (current mode logic) can be connected with a coupling network.

    Our circuit note CN-0422 has an example coupling network for CML<>LVDS using ADN4654 (HDMI uses CML for the physical layer TMDS data/clock); ADN4624 will be similar. So it might be useful to try and isolate the V-by-One inputs of THCV242 instead of the MIPI-CSI2 outputs, although ADN4624 will limit the bit rate to 2.5 Gbps maximum (the four channels should allow both V-by-One inputs though).

    The reason that it's challenging to isolate the MIPI-CSI2 directly is that as you mention, there are 1.2V signals used. In fact these are single-ended LVCMOS (1.2V) control signals, multiplexed on the same I/O lines as high-speed differential data (two single ended signals per differential pair). ADN4624 can only directly isolate the high-speed differential data, so to fully realize isolated MIPI-CSI2, a detection circuit to differentiate between HS positive/negative differential and the low power single ended signal states (00,01,10,11) would be needed, to control a MUX on the output side of ADN4624, as well as switching in a parallel isolation path for the 1.2V control signals using standard digital isolators (these only work down to 1.8V so level shifters would be required too). The timing requirements to handle the propagation delays for the ADN4624, level-shifters+standard isolator, and isolated control signal and MUX would all have to be considered.

    Overall trying to isolate V-by-One directly is probably a better option if the interface is short (ADN4624 has no RX eq) and can be capped at 2.5 Gbps.

    Best regards,

    Conal

Children
  • Hi ConalW

    Thanks for the valuable feedback. 

    ->Overall trying to isolate V-by-One directly is probably a better option if the interface is short (ADN4624 has no RX eq) and can be capped at 2.5 Gbps.

    As you recommended is it possible to go in between the V-by-One serializer and deserializer. 

                                                 

              Serializer THCV243  (THine)  --> ADN4624 (Analog Isolator) --> Deserializer THCV242 (THine)
             

    Our Maximum data rate would be 2.2Gpbs.

    So, Shall I conclude that ADN4624 can be used for CML signals? In between serializer and deserializer. 

    The differential mode output voltage of the serializer is 300mV. 

    I like to know we need to check any other parameter ADN4624 for confirmation

    Or do I need to add additional circuitry as recommended in-circuit note CN-0422 has an example coupling network for CML<>LVDS using ADN4654. 

                                                    

    Thanks

  • +1
    •  Analog Employees 
    on Aug 6, 2021 11:11 AM in reply to Praveen99

    Hi Praveen,

    Yes, with ADN4624 used in the serialized CML link, you will require a coupling network similar to CN0422 for ADN4654 (i.e. for that circuit, ADN4624 can be used instead for high bit rate/resolution with HDMI/TMDS).

    The coupling can be simplified - 10 nF AC coupling of both the input and output, but the output doesn't need the resistor biasing shown in CN0422 (assuming the THCV242 receiver can bias the lines). The input can be simplified also to 50 Ohm pull-ups after the AC coupling rather than before. This provides 100 Ohm differential termination, as well as 50 Ohm to supply for CML, but the supply voltage should suit the LVDS receivers (1.2V optimal) and the THCV243 drivers. You could try simply using the 1.8V supply of ADN4624 as a compromise to keep the resistor biasing simple (compared to CN0422).

    Regards,

    Conal