Hello there,
We are using the LTC4331 in our equipment, but randomly, our master receives NACK signals after sending a slave address. These slave addresses has been correctly acknowledged over few previous transactions, and the problem is manufacturer and model independent.
Our I2C is here cadenced at 93kHz, but similar issues happens at 90kHz. Our master MCU does not provide straight 100kHz due to silicon issues.
To look for faulty transactions, we flooded the I2C with transactions. Our test code does the following I2C transactions, in a loop, with 326µs between each transactions:
For i in 0 to 7 loop
I2C_Write(real_slave_addr(i), register_addr); // Register address is the same for all I2C peripherals
data = I2C_Read(read_slave_addr(i), 1); // Reads only one byte.
end loop;
When probing both SCL and SDA signals on both sides, we observe the following behaviours:
Case 1: incomplete I2C transaction.
Left: Master side of the I2C bus. In blue SDA, in yellow SCL. Please note the NACK at the end of the transaction.
Right: Slave side of the I2C bus. In yellow SDA, in blue SCL. Removing the Manchester-like encoding, we obtain the same beginning of data packet. However, only 6 SCL periods are here propagated.
Case 2:master side gets a NACK when sending the peripheral address, while the slave side continues to read data
Left: Master side of the I2C bus. In blue SDA, in yellow SCL. Please note the NACK at the end of the transaction.
Right: Slave side of the I2C bus. In yellow SDA, in blue SCL. At the opposite of the master side, we obtain here a complete read transaction over more than 8-bit.
Investigation for both cases
When such NACK appears, we directly read the fault register of the master side LTC4331. What we get are both I2C_WRITE_FAULT and EXT_I2C_FAULT.
What we mainly observe is:
- sometimes the slave side LTC4331 continues to emit a clock and data on its respective side, while the LTC4331 on the master has already answered a NACK.
- sometimes the slave side LTC4331 only emits 6 clock period and then stop the transmission. The appropriate NACK is following on the master side.
- sometimes, the NACK signal is alone, i.e. appears after more than 400µs.
Our hardware implementation involves the transmission over a 3-meter Ethernet cable, with bias resistors only on the emitter side. Receiver bias resistors have been not populated because we have a common ground on both sides of the Ethernet cable.
Could you please give us some clues of what would cause such failures?
Thank you for your assistance.
Best regards,
--
Niels
