ADUM4121 (Vout does not turn off normally)

I bought a GaN driver (ADUM4121) from ADI company for GaN short circuit test.

 Figure 1 in the attachment is the schematic diagram of short circuit test. The principle of the whole short circuit is: first supply power to the left and right of adum4121 driver; then use high voltage source to charge the 200uf DC capacitor; finally use function generator to control the PWM driving the left side to realize the output of driving the right side Vout.


Figure 2 in the attachment is the circuit diagram I built (PCB is made according to the circuit diagram).


Figure 3 in the attachment is the problem I found during the short circuit test: when the voltage supplied by the high voltage source exceeds 100V, the PWM waveform channel 4 (2us length) on the left side of the drive can be normally turned off; however, the Vout signal (channel 3) on the right side of the drive can only be turned off after several hundred us.

 In my opinion, under normal conditions, the left PWM should be turned off, and the right Vout signal should also be turned off. PWM and Vout will not have such a large delay.

 thank you!

Parents
  • 0
    •  Analog Employees 
    on Mar 17, 2021 4:09 PM

    Hello,

    You are correct that this is abnormal activity. I have a few questions to start this analysis:

    1) Is VDD2 powered with a floating supply?

    2) How large of a voltage spike is seen on Vshunt? (ie, what resistance is being used?)

    3) Is Vgs measured with a differential probe?

    4) Is Vgs measured between the GaN Vgs above the shunt?

    5) Can we get a waveform of Vshunt during this time?

    Thanks,

    RSchnell

Reply
  • 0
    •  Analog Employees 
    on Mar 17, 2021 4:09 PM

    Hello,

    You are correct that this is abnormal activity. I have a few questions to start this analysis:

    1) Is VDD2 powered with a floating supply?

    2) How large of a voltage spike is seen on Vshunt? (ie, what resistance is being used?)

    3) Is Vgs measured with a differential probe?

    4) Is Vgs measured between the GaN Vgs above the shunt?

    5) Can we get a waveform of Vshunt during this time?

    Thanks,

    RSchnell

Children
  • Hello,RSchnell

    I'm glad to hear from you。

    1) VDD2 is powered directly by a voltage source(Do LDO and DC-DC power modules need to be added to the driver?)

    2) The resistance is a coaxial shunt(SSDN-10mOhm)

    3) VGS is detected with a passive probe(TPP0201)

    4) VGS is the measured gate source voltage of Gan devices

    5) Fig. 1 is the waveform when VDS = 50V (theoretically normal waveform) , and Fig. 2 is the waveform when VDS = 100V(The Vout on the right side of the drive can't be turned off normally. I set the PWM pulse width of 2us)

     Fig.1  Fig.2