LTM2881 & LTM2882 EMI ISSUE

Hello Aihua, 

The high emission levels between 300MHz and 600MHz suggest that common mode noise on the secondary side of your PCB does not have an effective low impedance return path back to the primary side of your PCB. Stitching capacitance across the isolation barrier is used to provide a low impedance return path for common mode noise. Discrete stitching capacitors are useful up to around 300MHz, but for EMI suppression above 300MHz, an embedded stitching capacitor using the PCB planes is more effective. 

Does your PCB have the embedded stitching capacitor approach detailed in these user guides, (see layer 1 and layer 2 on page 4)

https://www.analog.com/media/en/dsp-documentation/evaluation-kit-manuals/dc1747af.pdf

https://www.analog.com/media/en/dsp-documentation/evaluation-kit-manuals/dc1746af.pdf

Regards,

Neil

Dear Neil,

   PCB shown as below :

C9 C10 uses other capacity values(100pF,20pF), the test results are worse.

C9 C10 Series connection  and change to parallel connection,the test results are still worse.

Then C9 place 470pF,C10 short on top layer, add 470pF between secondary side and primary side on bottom layer,the test results are below the limit.

Plan to relayout ,Are there any suggests? Thanks~

Aihua

Hi Aihua, 

Thank you for sharing layout details. How many layers are in your PCB?  Are all metal layers visible in the image you have shared? 

The C9 and C10 capacitors are effective for reducing radiated emissions up to 300MHz. Above 300 MHz, the ESL of C9 and C10 makes these less effective as stitching capacitors. The experiment with parallel capacitors on top and bottom of the board will also reduce the ESL and help lower emissions, as you have shown.

The DC1746A and DC1747A demo boards also include an embedded stitching capacitor to suppress emissions above 300MHz. The metal on layer 1 and layer 2 form a parallel plate capacitor with very low ESL and a high self resonant frequency. You can see the overlapping layer 1 and layer 2 demo on page 4 of the demo board document linked above. 

If you will relayout the PCB, adding an embedded stitching capacitor would be better, if your PCB has enough layers. 

This application note has more details on using the PCB layers are a stitching capacitor. 

https://www.analog.com/media/en/technical-documentation/application-notes/AN-0971.pdf

Regards,

Neil 

Dear Neil,

Thanks for your help,This information is very useful about stitching capacitor~

1.The pcb is designed as 2layer, it has no isolated ground planes on inner layer.all metal layers are shown in the image. I also see same information on LTM288x application,The embedded capacitor effectively suppresses emissions above 400MHZ, but the insulation voltage of PCB is 2500V, I'm worried about the impact of insulation voltage,PCB substrate stack up can't meet the requirements(2500V).This has been confirmed with PCB factory. 

Can the demo boards (DC1746A and DC1747A) meet this requirement(2500V)? it has no any information about pcb stack up.

2. During EMI debug,  C9 place 470pF, C10 short and place some smaller capacitance(100pF/10pF) on bottom layer(parallel connection of different capacitors), the test results are worse. It seems better to choose a larger capacitance.But the capacitors are difficult to choose.So I plan to relayout  as your advice, adding an embedded stitching capacitor.

BR

Aihua

Hi Aihua, 

The insulation requirements for the PCB depend on the application for your product and the relevant safety certification standards. 

More most safety certifications, an plane to plane spacing (in the z-direction) of 0.4mm is sufficient for reinforced insulation. The 2500V isolation target suggests to me that this is used in a basic insulation system. 0.4mm should be sufficient for basic insulation systems.

The DC1746A and DC1747A boards use a "floating stitching capacitor" method where there are two insulation barriers in series. The layer 1 to layer 2 spacing s 8mil / 0.2mm in thickness, summing for a total thickness of 0.4mm through the two capacitors. The "floating stitching capacitor" method and the requirements around plane to plane spacing are discussed in the "Meeting Isolation Standards" of AN-0971 

I've attached the stackup here, I hope this is useful: 

PDF

Regards,

Neil 

Dear Neil,

       Thanks for your great supports~  I got it.

        I will re-layout and debug, If have any good news, I'll let you know. Thank you~

BR

Aihua

Hi Aihua, 

No problem, I am happy to help,

If you would like us to review your finished layout over email please let me know, 

Regards,

Neil 

Dear Neil,

     Thanks~ Please give me your email address. 

BR

Aihua

Hi Aihua, 

I've sent you a message with my e-mail address, 

Regards,

Neil 

Hi Aihua, 

I've sent you a message with my e-mail address, 

Regards,

Neil