LTC4316 XORL translation voltage

Hi,

I'm using the LTC4316 I2C address and voltage translator for the first time in a product re-design. For system reasons, the incoming I2C bus is 5V TTL, and the 4316 Vcc is 3.2V.  XORL is defined as per the data sheet by a 1% resistor pair from Vcc to GND, decoupled with a 1nF ceramic capacitor. XORH is grounded.

I am finding that the addresses do not translate correctly, An example is a divider of 28K0 and 100K, giving a ratio of 0.78125, exactly the ratio shown in the data sheet to generate an XOR on address bits 3 and 2. However, the translated I2C output has bits 3,1,0 flipped rather than 3,2. When I measure the XORL voltage as a fraction of the supply using a 7-digit DVM in ratiometric mode, it shows 0.78124. I checked that there was no difference in I2C translation whether the DVM measurement leads were attached or not.

I attach a scope shot showing the I2C clock at the top, input I2C data in the centre and output I2c data at the bottom. The upper two traces are at 5V/div and the bottom one 2V/div. The timebase is 20us/div. Other data-sheet resistor ratios give similar but not identical errors. I noted that all observed translations imply a lower voltage at the XORL pin than is measured.

Can you suggest what might be the problem?

Thanks,

Peter

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  • An additional piece of information: the LTC4316 enable is held low by a reset line until well after the power rails are stable. The rising end of reset is the only occasion that the ADCs in the chip convert the voltages on the XORH and XORL pins. I have tried forcing additional low-going  pulses on the enable input in order to re-acquire the XORL voltage, but get the same result.

    Peter

  • This can't be a very interesting topic! Latest news:

    1) Since the XORL pin in my original design is decoupled to GND, this created a phase lag between any change in Vcc and the pin. Adding a capacitor from Vcc to the XORL pin having a value that mirrored the resistive divider ratio cured the problem (but see 2 below). The Vcc rail had normal mV perturbations on it due to the varying current demands of other parts of the circuit passing through PC track resistances, but these were not being ratioed correctly when there was only a single capacitor on XORL (to ground) with small changes in the rail voltage.

    2) The majority of the ratios using 1% resistors give the correct translation of the I2C addresses, but some values need more accurate ratios than implied in the data sheet. For example, a value for the upper resistor of 88.22K (86.6K + 1.62K) and a lower resistor of 100K (measured as 99.97K) gives a ratio of 0.531293, against the data sheet value of 0.53125 +/- 0.015. Using these values for the upper resistor gave a measured difference in the XORL/Vcc voltage ratio of -0.011 (i.e. within specification), but consistently resulted in an translation corresponding to the next bit pattern lower in the list. I would suggest that the error margins shown in the data sheet may be too relaxed, at least over some of their range. I can correct this particular instance by replacing the 1K62 resistor with a short circuit, but it does not meet the design tolerances.

    I hope this is of some use to others planning to use the LTC4316 series of parts.

    Peter