We are evaluating the ADuM4223.Let me ask you some questions.
① Is the output a CMOS structure?I am concerned about a short circuit in the power line of the internal structure.(2) It is written in the data sheet that the distance between the power supply pin and the bypass capacitor should be 5 mm or less.I want to know what happens if I don't.③ Is it OK to draw a pattern directly under the IC?
What kind of problem will occur if a pattern is drawn directly under the IC?
Thank you for your consideration.
1) The output of the ADuM4423 is a CMOS structure. There is a PMOS FET that provides the source current, and an NMOS FET that provides the sink current.
2) The 5 mm is a suggestion in order to reduce inductance between the decoupling and the gate driver IC. If the distance is too far, there will be more ringing on the output waveforms of the chip. If the distance is excessive, it is possible to get large ripples on the VDDA/B and GNDA/B pins that can cause brownouts. This would take distances in multiple centimeters. This is an issue that almost any gate driver would experience. Due to the large peak currents that are involved in the switching of power devices, it is important to have good decoupling to the gate driver IC.
3) If a metal trace is below the IC, the first concern is if there will still be adequate creepage/clearance for the isolation required of the system. Is the ADuM4223 going into a high voltage system? Is the ADuM4223 being used as a functional isoaltion barrier or a safety isolation barrier? The ADuM4223 will not suffer from having a trace eblow it, but the effective distance between the low voltage and high voltage sides of the parts will be reduced when there is any metal between the primary and secondary side pins.
Thank you for your answer.
There were several cases where ADuM4223 failed during the evaluation.Let me ask you an additional question.
Has there been a case where the output CMOS was latched up in the past?
Also, is there a possibility even if there is no case?What should I do if a latch-up occurs?I want to know the countermeasures.Also, if there is a non-CMOS(Output structure) product as an alternative, please introduce it.(Is a non-CMOS product with a wide (high) power supply voltage range?)