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ADuM1441 Power sequence between input and Output side supply

Hello

I'm using ADuM1441 in my design. From main power supply turning On time VDD2(output) power has delay of 500us. But VDD1(input) power takes around 2.6ms from main power supply turn on.

So ADuM1441 gets it's output power first compared input power and hence as per truth table output will be in it's default state which is high for ADuM1441.

This behaviour I'm seeing only in one board out of many boards manufactured. For other boards even with this powering time difference board is working fine.

To avoid such issues in production I need to make sure that power supplied to ADuM1441 and it's timing difference should be within certain margin which is acceptable for ADuM1441 and with which ADuM1441 never finds a failure case.

What is the worst case powering time difference between input(VDD1) and output(VDD2) supply of ADuM1441 which is acceptable.

Regards

Nidhi P Shetty

  • Hi Nidhi,

    When VDD2 is powered beyond the UVLO threshold, The part should go to the default high state and remain until it receives a signal from side 1. (Assuming Vix = Low, VDD1 unpowered, EN1/2 low). When power is restored to VDD1, the Outputs return to input state within 150 µs of VDDI power restoration.

    You can power side 2 first, there is no time difference which should cause the part to fail.

    So ADuM1441 gets it's output power first compared input power and hence as per truth table output will be in it's default state which is high for ADuM1441.

    - Note this is only the case when EN1/2 are low. See Table.21 of datasheet. Have you tied EN1/2 high or low in your application? Could you verify on the board you mention which does not work? If EN1/2 are tied high, then the outputs are the last state before input power is shut down. see Table.21

    Best Regards,

    Shane

  • Hi Shane

    Below is the ADuM1441 circuit that I have used in my design.

    Input and Output side power supply capture is as given below

    Yellow - VCC3_3.3V              Blue - AVDD_3.3V

    After powering ON the board, using some configurations I'm making all three GPIOs as high and then I observed same logic at the output as well. 

    I have retained all my GPIOs in previous power on state itself. Hence I tried verifying this.

    With my GPIO state being high, I turned OFF my board. When I turned on my board back on input side I'm seeing proper high logic but it is not reflected on output side. Power remains same as above capture.

    Please help me out in understanding the reason for this.

    Thanks and Regards

    Nidhi P Shetty