Hi ADI Expert,
My customer refer the CFTL CN0422 HDMI-isolation reference design to made their owe PCB, but failed at HDMI compliance testing and some monitor can't turn-on too.
The device configuration all the same as CN0422 720P/60Hz.
Blow as capture of HDMI compliance test report.
Item 2~4 source eye diagram fail, data jitter was out of spec.
Item 18~25 source low amplitude fail, out of spec 2.700V~ 2.900V
So I checked PCB layout again, Pls refer to PCB placement as blow, as you can see Skylake-U chips output TMDS signal as TMDS-1 trace first, which length around 3000mil than pass through a connector to isolation daughter board. TMDS-2 trace length around 2500mil passed through to ADN4654, than couple out iso-TMDS trace length around 1000mil.
Each of TMDS data0~2 and clk pairs are length equally.
I doubt of trace length and connector attenuation effect, may I have your comment of this issue, thanks.
I have just sent you an email,
It looks like a reflection on the line could be causing the eye diagram to fail,
The reflection is measured on the HDMI output which would lead me to believe the issue is at the connection from the isolators to the HDMI output connector, rather than from the Skylake chip to the isolators. Any reflections from the Skylake processor to the CN-0422 circuitry would be filtered out by the CN-0422 and you wouldn’t observe it on the compliance eye diagram at the HDMI output.
The ADI eye diagram results are available here at the CN-0422 circuit note, Figure 4 shows the results at 720p, which does not show the same reflection
On the some monitors not turning on, I believe the problem is more likely to be the hotplug detect and not the TMDS lines. There is a sensitivity with the design which arises from the ADuM1250 I2C isolators being used for the HPD signal; the I2C pullup resistor means that HPD line is always asserted. Strictly speaking the HPD should only be asserted when a sink is connected. Most monitors can handle this but we have observed a small subset of monitors where this causes a problem.
To check if this is the issue, you can use a wire to temporarily short the Skylake side of the HPD line to ground, when the short is released you can check does this cause the monitor to display correctly.
The solution for this HPD issue would be to use a standard digital isolator with a push-pull output to connect the HPD from the sink to the source, rather than an ADuM1250 I2C isolator with its open-drain output + pullup resistor. ADuM110N would be a good option for a standard digital isolator.
Thanks for your comments, since to doubt of PCB layout for our hardware design, thus customer does more testing.
First, pass through LVDS isolation, hardware removed ADN4654 with CML-LVDS/LVDS-CML circuits and TMDS links pass through.
There are testing report as blow,
1. Bypass Isolation IC (ADN4654B), eye diagram passed, resolution: 720P
2. Non-Bypass Isolation (ADN4654B), eye diagram failed, resolution: 720P
It showed non-isolation passed eye-diagram of 720P and 800x600 resolution.
Isolation design failed eye-diagram of 720P and 800x600 resolution.
Therefore PCB layout can passed eye-diagram when non-isolation condition, May I have your comments for the testing?
The reduced signal amplitude on the isolated output eye diagram vs the non-isolated output eye diagram is expected; the ADN4654 LVDS isolators provide a typical differential output voltage of 310mV which is less than the 400mV typical output from a dedicated TMDS transmitter output.
The reflection on the isolated output eye diagram is not expected, we have not observed this when testing the EVAL-CN0422-EBZ board. The isolated design may have an impedance discontinuity in the transmission line between the ADN4654 outputs and the HDMI connector. The AC coupling capacitors would be a likely culprit, these should be placed as close to the ADN4654 as possible to minimize any line reflections.
If the customer is happy to share this section of the schematic and layout by email and we can review internally.
May I have your mail address that I can share design files to you, thanks. Ray.
I have shared design file to you via mail few days ago, May I have your commands, thanks.