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Digital isolator behaviour with miso signal


I'm using ADuM1441 in my design.  I'm using SPI interface in my design which passes through ADuM1441 digital isolator. 

It passes mosi clock and chip select properly from mcu to slave.  I have connected miso to vid of ADuM1441(slave side) and vod to output of ADuM1441 which connected to mcu.

I'm seeing below miso signal across vid

Vod signal is as given below

Why the logic level at vid got changed at vod

This change is not accepted in my design

Please help me out 


Nidhi P Shetty