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Digital isolator behaviour with miso signal


I'm using ADuM1441 in my design.  I'm using SPI interface in my design which passes through ADuM1441 digital isolator. 

It passes mosi clock and chip select properly from mcu to slave.  I have connected miso to vid of ADuM1441(slave side) and vod to output of ADuM1441 which connected to mcu.

I'm seeing below miso signal across vid

Vod signal is as given below

Why the logic level at vid got changed at vod

This change is not accepted in my design

Please help me out 


Nidhi P Shetty

  • Hello Nidhi,

    This is definitely problematic behavior.  I believe the best place to start trouble shooting the problem is always with the power system.  Please verify the Vdd and Gnd connections are proper and that the bypass is connected correctly. 

    This looks like bus contention.  Do you have several MISO lines connected together in your design?  A quick test is to unsolder the Vod pin and lift it off of the board, then check that the proper signal is present.  If so, it looks like two outputs are connected together and it is making a voltage divider with the output impedance of the pin.

    If you need further support, please provide a section of your schematic.  We can arrange a direct communication if it is proprietary. 

    Best Regards,


  • Hi MSCantrell

    Thanks for the answer. You were correct that MISO is connected to two digital isolators. Which means two output pins are connected together. When removed one connection from this logic level was proper.

    Please find the image in below link.

    As per this I'm using 2 digital isolators (ADuM1441). Input side of both digital isolator always get power and enable.With respect to output power there can be two option.

    1. Output power and enable for first digital isolator is available(3.3V) and for second digital isolator it is not available(0V)

    2. Output power and enable for both digital isolators are available(3.3V)

    In both of the above cases MISO will come from two different ICs separately to VID pins of two different isolators .

    But VOD of both digital isolators shorted together causing logic level issues. How can I solve this issue without adding major changes in design.

    Please help me out.


    Nidhi P Shetty

  • Hello Nidhi,

    I could not view the schematic, however this issue must be addressed in many applications.  In a native SPI application there will be an enable line for each channel.  When the channel is disabled, the MISO line goes to high Z to enable what you are trying to do.  In the ADuM144x, the enable line works differently than most of our other isolators, it controls refresh, not output enable.  If you were using a different isolator, you could simply disable the unused channel.  Removing power from side 1 is problematic id you have signals at the output, since they will parasitically power the device and you could get unpredictable behavior.

    I think you have two options.

    1) If your current device is in the QSOP package you can change to the pin compatible ADuM141DBRQZ and connect the Enable lines to your processor.  This part consumes more power than the ADuM144x, but that may be acceptable.

    2) you can add a 2-1 digital mux and control it with a single line form your processor.  There are very small ones available.

    I hope this helps,

    Best Regards,

    Mark Cantrell

  • Hi Mark Cantrell

    As my PCB is already there I cannot go with second option.
    Attached with schematics.
     But I do not have GPIO control for enable lines. It is tied high directly. Hence whenever power is available it will get enable. 
    Below are the points with respect to my schematics.
    1. 3V3_EXT, VCC_3.3V is always available on power ON.
    2. IODVDD is available when DAC 2 is used.
    3. There is no GPIO control for enable pins.
    So when IODVDD is OFF I don't want MISO to get disturbed.
    I'm planning to use ADuM141E1 in 16-QSOP package in place of U25. Please confirm whether my understanding is correct.
    1. When IODVDD is OFF both VDDO and Vexoutput are Unpowered and VDDI and Vexinput are powered and enabled respectively. Then signals in U25 becomes 
    1. SCLK_DAC_Passive , MOSI_DAC_Passive will become indeterminant.
    2. MISO_DAC_Passive will be high/ Z .
    Please correct me if I'm wrong.
    As my DAC2 is in powered OFF condition "indeterminant state at it's pins can cause problems.
    Please confirm whether my understanding is correct.
    Nidhi P Shetty
  • Hi Mark Cantrell

    I'm waiting for your inputs.


    Nidhi P Shetty

  • Hello Nidhi,

    Unfortunately modulating power on the secondary side will not be adequate.  Each side of our devices operates independently.  The VOD pins are active if power is applied to side 1 of our device.  If there is no power on the secondary, the output on side 1 will not go to high Z in the ADuM141D, it will go to its default state, and that is still actively driven.  Switching to the ADuM141D0BRZ for example, will make the chip connected to DAC2 drive a 0 at its output when the power is not present on Vdd2, and you will have the same problem it will fight with the DAC 1 signal.  This approach depends on an enable signal from micro selecting the channel that you want to communicate with.

    I have not been able to come up with a way to make this circuit operate without a control line or at least an extra logic gate.  If you have a gate or two available we could possibly switch to an ADuM142 and use the third channel to let the presence of power on IOVDD control the selection of the MISO line.  If you want to explore options in more detail we should move this discussion off line.

    Best Regards,