I am using ADM3251E for RS-232 and ADM2587 for RS-485 on a single PCB with one DB-9 connector on the isolated side. ADM3251E does have one GND2 pin 11 on the isolated side while ADM2587 does have 4 GND2 pins on the isolated side. I am using one common ground on the isolated side with ADM3251E pin 11 and ADM2587 pin 16 and 20 connected to this GND2(ISO). The Stitching capacitor on the ADM3251E goes between the GND and GND2(ISO) pin 11. While on the ADM2587 the Stitching capacitor is recommended to be connected between GND and GND2(ISO) pins 11 and 14.
How can I use one embedded stitching capacitor for both of these devices? I am trying to achieve a Class B compliant low noise design. What is going to be my arrangement for the ADM2587 pins 11, 14, 16, 20 and ADM3251E pin 11 for using one stitching capacitor for both to get a Class B compliant design.
Your arrangement above looks like a further improvement, I agree with your approach here.
In reality some of the noise from Pin 11 of the ADM3251 will couple through the leadframe of the ADM3251…
Thanks for your query,
Application notes AN-1109 gives good information on mitigating isoPower emissions in general, and AN-1349 includes detail on achieving class B for the ADM2587E, which might be useful.
I’d recommend the use of EMI suppression ferrites with the ADM2587E to maximise margin to Class B. These should be placed between the Pin 11+Pin14 net and the GND2 net, and between pin 12 and the VISO net, per Figure 18 in AN-1349. Taiyo Yuden BKH1005LM182-T and Murata Electronics BLM15HD182SN1 are the recommended ferrite beads for EMI suppression. A 100nF capacitor is required between Pin 11 and Pin 12.
Regarding passing Class B with both devices, Pin 11 of the ADM3251 should be connected to Pin 11+Pin 14 of the ADM2587E. On the isolated side, the embedded stitching capacitor should be connected to Pin 11+14 of the ADM2867E and to Pin 11 of the ADM3251E.
If using these EMI suppression ferrites, do not short pin 11 of the ADM2587E to Pin 16 or 20 of the ADM2587E, as this will short out the ferrite beads and render them ineffective.
With both devices, I would use the available area under both DUTs for the stitching capacitor. The larger overlap will create a large and more effective stitching capacitance. I’d also recommended minimizing the size of the GND2 net if possible.
A rough sketch is below, where the blue represents one layer of the stitching capacitor,
Your response and details are greatly appreciated. I am using a similar approach for the stitching capacitor as shown in your sketch but I am using a ferrite bead(similar in value like L2) between pin 11 of ADM3251E and GND ISO. Also in my arrangement the GND ISO form ADM3251E is connected to the GND2 on ADM2587E. My sketch is shown at the end of this message with red connections.
In your sketch when you connect the pin 11 on ADM3251E and pin 11 on ADM2587E to the stitching capacitor then it does make a short across L2 then do we still use the L2 in the circuit?
I look forward to hear your response on my arrangement and your arrangement where L2 seems to be shorted with the stitching capacitor.
In reality some of the noise from Pin 11 of the ADM3251 will couple through the leadframe of the ADM3251 onto the VISO, V+, and V- supplies of the ADM3251. A further recommendation I would have is keeping these traces short and avoid connecting to any metal floods if possible. Smaller metallization will be a less effective antenna at radiating high frequency noise. Related to this, the capacitors C1, C2, C3 and C4 for the ADM3251E, and C1 for the ADM2587E should be kept as close to the device as possible.
Avoiding metal connections is not practical for the VISOOUT node of the ADM2587E, as it must be connected to the VISOIN pin, or for the GNDISO node as ground is commonly needed to be routed elsewhere. This is where the ferrites beads, as you have in your suggested design above, are important for EMI suppression.