(ADuM1281) Supply current

Hi !

I have a question about ADuM1281 supply current.
I was reading ADuM128x datasheet.

Datasheet says that IDDI(Q) = 0.8mA_max and IDDO(Q) = 2.0mA per Channel

This means, if I use ADuM1281 and input nothing,

IDD1 = 0.8mA(B Channel) + 2.0mA(A Channel) = 2.8mA

IDD2 = 0.8mA(A Channel) + 2.0mA(B Channel) = 2.8mA

Q1)

Is my understanding correct?

Q2)

Also datasheet says that if we input 1Mbps, IDD1 = 2.6mA_max and IDD2 = 2.9mA_max.

These value are smaller than quiescent current.

Why this happen?

Best regards

Kawa

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  • +1
    •  Analog Employees 
    on Jan 7, 2020 8:25 PM

    Hello Kawa,

    Your understanding is basically correct, but there are other things going on that can throw the values off a bit.

    First, there is a refresh circuit in the data path that runs at 1Mbps, and we do the test at 1Mbps.  This was actually a poor choice of test frequency since there can be beat effects between the data and refresh that can throw off the current that is measured.  I actually don't think this is why the max numbers do not line up, but it may contribute.

    When the test engineers measure these values, the max numbers are over the entire operating temperature range, and the numbers in Table 3 are what determines the pass fail criterion for the part at production.  They apply extra margins to these numbers to cover the wide temp range and product variability.  The typicals are really typical, but the maximums are conservative.  The values in table 2 are measured separately and the maximums are again determined statistically, but I don't think they have as much margin, they are more realistic to the actual performance of the part.  It is sometimes difficult to make everything line up exactly.

    I hope this helps with any issues.

    Best Regards,

    MSCantrell

  • Hi MSCantrell

    Thank you for your reply.

    I understood.

    What I wanted to check the most is whether the IDDQ specifications are for each channel of Achannel and Bchannel, or whether they indicate IDD1 and IDD2.

    I understood it for each channel, so I understood the content.

    Best regards

    Kawa

  • 0
    •  Analog Employees 
    on Jan 8, 2020 4:03 PM in reply to donadona999s

    Hello Kawa,

    Table 3 is on a port per side basis.  In other words, an input on side 1 will generate the specified amount of current to the side one Vdd pin.  You need to add them up to figure the full current.

    Table 2 is total power for each side under the specified condition. no adding anything up as long as all of the inputs are operating at the same frequency.  If you have fast and slow channels, you can do some arithmetic to figure it out. 

    Best Regards,

    MSCantrell

  • Hi MSCantrell

    Thank you for your reply.

    I understood that my understanding is correct.

    Thank you again.

    Best regards

    Kawa

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