I'm using the ADM3260 in a new design. VDD primary = 5V Visol. = 5V The output level(SDA and SCL) at the line (isolated output) signal swing is 5V to 800mV. I have a 1k5 pull-up on both SDA and SCL. I've measured the output relative to the ADM3260 Isolated Gnd. The input logic SDA and SCL signal swing is 5V to 0V.
How do I reduce GND offset? Why do i have 800mV GND offset?
The short answer is that this is expected operation. The offsets prevents a logic low latch-up in the I2C isolator. This video on the ADI website gives a more detailed description. Its applicable to the ADM3260, the ADuM1250 and the ADuM2250 isolators.