(ADuM3190)Open short test

Hi !

I have some question about ADuM3190

Our customer are using ADuM3190 for automotive application.

They perform all pin open short tests during acceptance testing.

***************************************************************************************************************************************

Q1)

I recognize that the power supply of VREF is supplied from VREG inside the device on both the primary side and the secondary side, right?

Q2)

Our customer test "Open short test" at 1V.

And they set the limit value between 20 and 50uA.

Also they do this test at -40deg and 25deg and 125deg.

Would this limit make sense?

Or should they set higher  limit value?

https://ez.analog.com/interface-isolation/f/q-a/86884/adum1280-adum1281-adum3190-can-you-tell-me-the-esd-diode-circuit-for-each-device/162604#162604

Because I heard that we can input to 1mA.

Q3)

What is the voltage range where the circuit downstream of Vreg starts operating (current consumption increases)?

Q4)

Do you have distribution data of Vreg applied voltage-Vreg injection current characteristics around 0-1.5V?

Q5)

Is it possible to disclose the voltage condition and current limit value of the pin open short test that ADI conducts at the final shipment inspection?

They need -40deg, 25deg, 125deg informations.

***************************************************************************************************************************************


We already know that some pins have ESD diode to each VREG.

When our customer check some pins(e.x. VREF1/2, Eaout, IN+, IN-, COMP) some device result are little bit high.

We speculate that the current is flowing through the protective diode and that the device is moving a little.

Most devices fall within their specifications (2-50uA), but about 0.3% shows results exceeding 100uA.

So they want to know what they are doing is correct or not.


Best regards

Kawa



Add comments
[edited by: donadona999s at 6:20 AM (GMT 0) on 5 Sep 2019]
Parents
  • 0
    •  Analog Employees 
    on Sep 5, 2019 7:14 PM

    Hello Kawa

    Q1)

    I recognize that the power supply of VREF is supplied from VREG inside the device on both the primary side and the secondary side, right?

    A1) VDDx is derived from VBUSx through an internal Regulator, unless they are tied together, which disables the regulator and simply uses the applied voltage to power the chip.  If the two power pins are tied together they must be operated at 3.3V.

    Q2)

    Our customer test "Open short test" at 1V.

    And they set the limit value between 20 and 50uA.

    Also they do this test at -40deg and 25deg and 125deg.

    Would this limit make sense?

    Or should they set higher  limit value?

    A2) I spoke to the designer about this.  First I want to understand exactly what test is being done.  I am assuming you are grounding all pins except the pin under test, then applying 1V and measuring leakage.  If that is the case than leakage can come from a couple of sources, first the ESD diodes start to turn on at about 0.7V so there is sufficient voltage to cause some significant leakage.  Second some pins like UD+ and UD- have internal pull down resistors of 15kohm.  This means that there will be leakage and it will not be the same for all pins.  We have determined that 1mA through an ESD diode will not damage it.  We also can not guarantee the same leakage at this low voltages.  The diodes are not optimized for sharp turn on.  I would recommend reducing the test voltage to below 0.7V and see if the leakage (except for UD+ and UD-) goes away for the most part.  Setting a higher threshold is possible, but will not guarantee consistent results.

    Q3)

    What is the voltage range where the circuit downstream of Vreg starts operating (current consumption increases)?

    A3) It would require simulation to get this answer.  It is not a simple voltage regulator, there is extra circuitry to disable it when VBUS and VDD are the same.

    Q4)

    Do you have distribution data of Vreg applied voltage-Vreg injection current characteristics around 0-1.5V?

    A4) we do not have that data.  The part has been on the market for many years and at this point, it would be easier to take new data than find what data was taken on this.   This was not a parameter that we have a specification for

    Q5)

    Is it possible to disclose the voltage condition and current limit value of the pin open short test that ADI conducts at the final shipment inspection?

    A5) We do input leakage testing, but I believe this is an active test, not a check for shorts.  I am not sure it applies to your case.

    I hope this helps,

    Best Regards

    MSCantrell

  • Hi !

    Thank you for your reply.

    A1) VDDx is derived from VBUSx through an internal Regulator, unless they are tied together, which disables the regulator and simply uses the applied voltage to power the chip.  If the two power pins are tied together they must be operated at 3.3V.

    => I understood that if we use only VDD, device internal power supply would be VREG.

    I am assuming you are grounding all pins except the pin under test, then applying 1V and measuring leakage. 

    => I will confirm this to my customer.

    If that is the case than leakage can come from a couple of sources, first the ESD diodes start to turn on at about 0.7V so there is sufficient voltage to cause some significant leakage. 

    => I thought that if we input 1V to some piin (e.x. VREF1), voltage of VREG rises through the ESD protection element.

    And some circuit under VREG will be supplied from VREG and wil be litte bit on.

    Are saying the same thing?

    Second some pins like UD+ and UD- have internal pull down resistors of 15kohm. 

    =>Which pins are UD+ and UD-? I couldn't find that pins.

    We do input leakage testing, but I believe this is an active test, not a check for shorts.  I am not sure it applies to your case.

    =>What test is ADI doing?

    Usually, when conducting a final test or ATE, I think that an open-short test is always performed one pin at a time.

    Can you disclose the conditions?

    Or isn't an open-short test conducted?

    Best regards

    Kawa

Reply Children