We have implemented an isolated DVI port on one of our products using the ADuM1250 to carry the DDC channel [which is an I2C bus to all intents and purposes].
On a small % of units we are getting an issue where the ADuM1250 is outputting an invalid SDA signal to the chipset (connected to side 1) when the monitor side isn't properly powered.
This only happens during board power up (or reset), and wouldn't normally matter since no data transfer is happening. But the chipset samples this line to determine whether to enable the display output or not - so we need SDA to stay high until the time where we switch on the DC/DC that brings the side 2 (monitor side) rail up to 5V.
The side 1 connection goes to the chipset only (with the pullup). It's definitely the ADuM1250 driving the line since the 0.9V low level is unique and easy to spot.
The issue varies with different monitor types. The one I'm looking at just now provides enough (unwanted) backdrive power to hold the side 2 power rail at 1.74V when our box is off (or powering up). This should be below the UVLO in the ADuM, so we expected it to behave predictably and stay quiet waiting for side 2 power. [Side 1 is up normally and is 3.3V]
The issue doesn't happen at FIRST power up - where side 2 was raised from 0 to 1.7V by connecting the monitor. Only happens on later power cycles when side 2 went to 5V in the past and then down again to 1.7V. And certainly is very intermittent. Most units never show it.
The unit I'm working with this week has a temperature cliff edge on it. At room temp and below 60C, there are very rare low-going pulses on SDA1 (a few us each) - pretty harmless. Above 65C, SDA1 is low (0.9V) for >95% of the time - usually fatal. I cannot measure any variation in the side 2 power rail with temperature - it's rock solid at 1.74V.
The SDA2 is properly high (well equal to the side 2 power rail) throughout. Maybe there is a tiny amount of noise on it but its 10s of mV at most and I need to work on my probing to make sure I'm not seeing ghosts of the larger SDA1 signal that aren't real.
I can easily fix the issue (I hope...) by altering the power sequence to bring up the side 2 power before starting the chipset. What I'm looking for is a better understanding of why the ADuM1250 UVLO isn't working properly, which will give me confidence that fielded product will not malfunction in the future.
This sounds like a more involved debug where I'll ask for design details. Do you have a local Analog Devices FAE contact to work through?