We want to use ADUM140E0BRZ for digital isolator and we study AN-1109 for layout suggest. It suggest to use 4 -layer PCB and a thin core layer is used for the power and ground planes as below picture, If we want to use 8-layer PCB , How to plan our PCB stack? Does ADI has suggestion to us for PCB stack? Does GND layer and power layer need tightly ? Second picture is our PCB stack now.
the purpose of this suggestion is to form a low parasitic capacitor with PCB plane. it has better impedance characteristic at high frequency domain. it can help control the noise on power rail, then improve the emission performance. we would suggest to follow this instruction for a better emission results.
Thanks for your reply. Due to our PCB is 8 layer. May I change PCB stack as below picture , Do you have any suggestion? Thanks.
The following article shows the stack-up used for a six-layer board with multiple ADuM5411 devices, and may be a useful reference.
I'd also point out that the ADuM140 family exhibits much lower radiated emissions than previous generations, and has been demonstrated to pass EN55022 Class B limits at 5 Mbps with a simple 2-layer PCB (no stitching capacitance).